A high speed complex adaptive filter for an asymmetric wireless LAN using a new quantized polynomial representation. - Adesh Garg; Ian Steiner; Graham A. Jullien; James W. Haslett; G. H. McGibney (ISCAS (2), 2003)

A 1-Tap 40-Gb/s Look-Ahead Decision Feedback Equalizer in 0.18-$muhbox m$SiGe BiCMOS Technology. - Adesh Garg; Anthony Chan Carusone; Sorin P. Voinigescu (IEEE J. Solid State Circuits, 2006)

21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber. - Jun Cao 001; Bo Zhang 029; Ullas Singh; Delong Cui; Anand Vasani; Adesh Garg; Wei Zhang; Namik Kocaman; Deyi Pi; Bharath Raghavan; Hui Pan 002; Ichiro Fujimori; et al. (ISSCC, 2009)

A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber. - Jun Cao 001; Bo Zhang 029; Ullas Singh; Delong Cui; Anand Vasani; Adesh Garg; Wei Zhang; Namik Kocaman; Deyi Pi; Bharath Raghavan; Hui Pan 002; Ichiro Fujimori; et al. (IEEE J. Solid State Circuits, 2010)

11.3Gb/s CMOS SONET-compliant transceiver for both RZ and NRZ applications. - Namik Kocaman; Adesh Garg; Bharath Raghavan; Delong Cui; Anand Vasani; Keith Tang; Deyi Pi; Haitao Tong; Siavash Fallahi; Wei Zhang; Ullas Singh; Jun Cao 001; et al. (ISSCC, 2011)

11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications. - Namik Kocaman; Adesh Garg; Bharath Raghavan; Delong Cui; Anand Vasani; Keith Tang; Deyi Pi; Haitao Tong; Siavash Fallahi; Wei Zhang; Ullas Singh; Jun Cao 001; et al. (IEEE J. Solid State Circuits, 2011)

A 195mW / 55mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40nm CMOS. - Bo Zhang 029; Ali Nazemi; Adesh Garg; Namik Kocaman; Mahmoud Reza Ahmadi; Mehdi Khanpour; Heng Zhang; Jun Cao 001; Afshin Momtaz (ISSCC, 2013)

20.2 A 16TX/16RX 60GHz 802.11ad chipset with single coaxial interface and polarization diversity. - Michael Boers; Iason Vassiliou; Saikat Sarkar 001; Sean T. Nicolson; Ehsan Adabi; Bagher Afshar; Bevin G. Perumana; Theodoros Chalvatzis; Spyros Kavadias; Padmanava Sen; Wei Liat Chan; Alvin Hsing-Ting Yu; et al. (ISSCC, 2014)

2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS. - Ullas Singh; Adesh Garg; Bharath Raghavan; Nick Huang; Heng Zhang; Zhi Huang; Afshin Momtaz; Jun Cao 001 (ISSCC, 2014)

A quad-channel 112-128 Gb/s coherent transmitter in 40 nm CMOS. - Adesh Garg; Ullas Singh; Nick Huang; Wayne Wong; Bin Liu; Zhi Chao Huang; Afshin Momtaz; Jun Cao 001 (VLSIC, 2014)

A 780 mW 4 × 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS. - Ullas Singh; Adesh Garg; Bharath Raghavan; Nick Huang; Heng Zhang; Zhi Chao Huang; Afshin Momtaz; Jun Cao 001 (IEEE J. Solid State Circuits, 2014)

A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5-11.5 Gb/s Serial Links. - Bo Zhang 029; Ali Nazemi; Adesh Garg; Namik Kocaman; Mahmoud Reza Ahmadi; Mehdi Khanpour; Heng Zhang; Jun Cao 001; Afshin Momtaz (IEEE J. Solid State Circuits, 2015)

An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology. - Namik Kocaman; Ullas Singh; Bharath Raghavan; Arvindh Iyer; Kumar Thasari; Saurabh Surana; Jun Won Jung; Jaehun Jeong; Heng Zhang; Anand Vasani; Yonghyun Shim; Zhi Huang; et al. (ISSCC, 2022)

18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS. - Guansheng Li; Adesh Garg; Tim He; Ullas Singh; Jiawen Zhang; Lakshmi P. Rao; Chang Liu; Meisam Honarvar Nazari; Yang Liu; Yong Liu; Heng Zhang; Tamer A. Ali 001; et al. (ISSCC, 2024)

An 800GbE PAM-4 PHY Transceiver that Supports 42dB Copper and Direct-Drive Optical Applications in 7nm. - Chang Liu; Burak Çatli; Yong Liu; Anand Vasani; Guansheng Li; Kun Chua; Lakshmi P. Rao; Yang Liu; Xin Meng; Jiawen Zhang; Tim He; Batu Dayanik; et al. (CICC, 2025)