A simultaneous, radix four, I2L multiplier mechanized via repeated addition. - Adit D. Singh; James R. Armstrong (MVL, 1978)

Tree Structured Sequential Multiple-Valued Logic Design from Universal Modules. - Adit D. Singh; F. Gail Gray; James R. Armstrong (IEEE Trans. Computers, 1981)

On Area Efficient and Fault Tolerant Tree Embedding In VLSI. - Hee Yong Youn; Adit D. Singh (ICPP, 1987)

Near Optimal Embedding of Binary Tree Architecture in VLSI. - Hee Yong Youn; Adit D. Singh (ICDCS, 1988)

A Highly Efficient Design for Reconfiguring the Processor Array in VLSI. - Hee Yong Youn; Adit D. Singh (ICPP (1), 1988)

Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays. - Adit D. Singh (IEEE Trans. Computers, 1988)

Modelling correlated transient failures in fault-tolerant systems. - C. Mani Krishna 001; Adit D. Singh (FTCS, 1989)

An efficient channel routing algorithm for defective arrays. - Hee Yong Youn; Adit D. Singh (ICCAD, 1989)

A Near Optimal Adaptive Row Modular Design for Efficiently Reconfiguring the Processor Array in VLSI. - Hee Yong Youn; Adit D. Singh (ICPP (1), 1989)

A single cached copy data coherence scheme for multiprocessor systems. - Abraham Mendelson; Dhiraj K. Pradhan; Adit D. Singh (SIGARCH Comput. Archit. News, 1989)

On Implementing Large Binary Tree Architectures in VLSI and WSI. - Hee Yong Youn; Adit D. Singh (IEEE Trans. Computers, 1989)

Fault Tolerance in VLSI Circuits. - Israel Koren; Adit D. Singh (Computer, 1990)

Fault-Tolerant Systems - Guest Editors' Introduction to the Special Issue. - Adit D. Singh; Singaravel Murugesan (Computer, 1990)

On Optimizing Wafer-Probe Testing for Product Quality Using Die-Yield Prediction. - Adit D. Singh; C. Mani Krishna 001 (ITC, 1991)

A Modular Fault-Tolerant Binary Tree Architecture with Short Links. - Adit D. Singh; Hee Yong Youn (IEEE Trans. Computers, 1991)

Yield optimization in large RAM's with hierarchical redundancy. - Kumar N. Ganapathy; Adit D. Singh; Dhiraj K. Pradhan (IEEE J. Solid State Circuits, 1991)

Chip Test Optimization Using Defect Clustering Information. - Adit D. Singh; C. Mani Krishna 001 (FTCS, 1992)

Analysis of the die test optimization algorithm for negative binomial yield statistics. - C. Mani Krishna 001; Adit D. Singh (VTS, 1992)

Adaptive Voting for Faulty (VFF) Node Scheme for Distributed Self-Diagnosis. - Jae Young Lee 008; Hee Yong Youn; Adit D. Singh (FTCS, 1993)

The effect of defect clustering on test transparency and defect levels. - Adit D. Singh; C. Mani Krishna 001 (VTS, 1993)

On optimizing VLSI testing for product quality using die-yield prediction. - Adit D. Singh; C. Mani Krishna 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Incorporating IDDQ testing in BIST: improved coverage through test diversity. - Adit D. Singh; Jason P. Hurst (VTS, 1994)

ADTS: an array defect-tolerance scheme for wafer scale gate arrays. - Adit D. Singh (DFT, 1995)

IDDQ Testing of CMOS Opens: An Experimental Study. - Adit D. Singh; Haroon Rasheed; Walter W. Weber (ITC, 1995)

A differential built-in current sensor design for high speed IDDQ testing. - Jason P. Hurst; Adit D. Singh (VLSI Design, 1995)

An experimental evaluation of the differential BICS for IDDQ testing. - Walter W. Weber; Adit D. Singh (VTS, 1995)

Adaptive Unanimous Voting (UV) Scheme for Distributed Self-Diagnosis. - Jae Young Lee 008; Hee Yong Youn; Adit D. Singh (IEEE Trans. Computers, 1995)

On the Effect of Defect Clustering on Test Transparency and IC Test Optimization. - Adit D. Singh; C. Mani Krishna 001 (IEEE Trans. Computers, 1996)

An IDDQ Sensor for Concurrent Timing Error Detection. - Christopher G. Knight; Adit D. Singh; Victor P. Nelson (DFT, 1997)

Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study. - Adit D. Singh; Phil Nigh; C. Mani Krishna 001 (ITC, 1997)

Incorporating IDDQ Testing with BIST for Improved Coverage: An Experimental Study. - Walter W. Weber; Adit D. Singh (J. Electron. Test., 1997)

Binning for IC Quality: Experimental Studies on the SEMATECH Data. - Adit D. Singh; David R. Lakin II; Gaurav Sinha; Phil Nigh (DFT, 1998)

A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing. - Egor S. Sogomonyan; Adit D. Singh; Michael Gössel (VTS, 1998)

Exploiting defect clustering to screen bare die for infant mortality failures: an experimental study. - David R. Lakin II; Adit D. Singh (ITC, 1999)

Testability evaluation of sequential designs incorporating the multi-mode scannable memory element. - Adit D. Singh; Egor S. Sogomonyan; Michael Gössel; Markus Seuring (ITC, 1999)

Yield-Reliability Modeling for Fault Tolerant Integrated Circuits. - Thomas S. Barnett; Adit D. Singh; Victor P. Nelson (DFT, 2001)

Estimating burn-in fall-out for redundant memory. - Thomas S. Barnett; Adit D. Singh; Victor P. Nelson (ITC, 2001)

Burn-In Failures and Local Region Yield: An Integrated Yield-Reliability Model. - Thomas S. Barnett; Adit D. Singh; Victor P. Nelson (VTS, 2001)

Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging. - Egor S. Sogomonyan; Andrej A. Morosov; Jan Rzeha; Michael Gössel; Adit D. Singh (VTS, 2001)

Redundancy Implications for Early-Life Reliability: Experimental Verification of an Integrated Yield-Reliability Model. - Thomas S. Barnett; Matt Grady; Kathleen G. Purdy; Adit D. Singh (ITC, 2002)

Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction. - Thomas S. Barnett; Adit D. Singh; Matt Grady; Kathleen G. Purdy (VTS, 2002)

Scan-Path with Directly Duplicated and Inverted Duplicated Registers. - Michael Gössel; Egor S. Sogomonyan; Adit D. Singh (VTS, 2002)

IC Reliability Simulator ARET and Its Application in Design-for-Reliability. - Xiangdong Xuan; Abhijit Chatterjee; Adit D. Singh; Namsoo P. Kim; Mark T. Chisa (Asian Test Symposium, 2003)

Integrating Yield, Test and Reliability: "Statistical Models with Applications to Test and Burn-in Optimization". - Adit D. Singh (ISQED, 2003)

Relating Yield Models to Burn-In Fall-Out in Time. - Thomas S. Barnett; Adit D. Singh (ITC, 2003)

Should Nanometer Circuits be Periodically Tested in the Field? - Adit D. Singh (ITC, 2003)

Experiments in Detecting Delay Faults using Multiple Higher Frequency Clocks and Results from Neighboring Die. - Haihua Yan; Adit D. Singh (ITC, 2003)

Multimode scan: Test per clock BIST for IP cores. - Adit D. Singh; Markus Seuring; Michael Gössel; Egor S. Sogomonyan (ACM Trans. Design Autom. Electr. Syst., 2003)

Extending integrated-circuit yield-models to estimate early-life reliability. - Thomas S. Barnett; Adit D. Singh; Victor P. Nelson (IEEE Trans. Reliab., 2003)

Reduce Yield Loss in Delay Defect Detection in Slack Interval. - Haihua Yan; Adit D. Singh (Asian Test Symposium, 2004)

Application of local design-for-reliability techniques for reducing wear-out degradation of CMOS combinational logic circuits. - Xiangdong Xuan; Abhijit Chatterjee; Adit D. Singh (ETS, 2004)

Sizing CMOS Circuits for Increased Transient Error Tolerance. - Yuvraj Singh Dhillon; Abdulkadir Utku Diril; Abhijit Chatterjee; Adit D. Singh (IOLTS, 2004)

Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation Study. - Haihua Yan; Adit D. Singh (ITC, 2004)

Low-power dual Vth pseudo dual Vdd domino circuits. - Yuvraj Singh Dhillon; Abdulkadir Utku Diril; Abhijit Chatterjee; Adit D. Singh (SBCCI, 2004)

Low-power domino circuits using NMOS pull-up on off-critical paths. - Abdulkadir Utku Diril; Yuvraj Singh Dhillon; Abhijit Chatterjee; Adit D. Singh (ASP-DAC, 2005)

T2: Statistical Methods for VLSI Test and Burn-in Optimization. - Adit D. Singh (Asian Test Symposium, 2005)

Delay Defect Characterization Using Low Voltage Test. - Haihua Yan; Adit D. Singh; Gefu Xu (Asian Test Symposium, 2005)

A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS. - Maryam Ashouei; Abhijit Chatterjee; Adit D. Singh; Vivek De (ICCD, 2005)

Low Voltage Test in Place of Fast Clock in DDSI Delay Test. - Haihua Yan; Gefu Xu; Adit D. Singh (ISQED, 2005)

A random access scans architecture to reduce hardware overhead. - Anand S. Mudlapur; Vishwani D. Agrawal; Adit D. Singh (ITC, 2005)

A self-timed structural test methodology for timing anomalies due to defects and process variations. - Adit D. Singh (ITC, 2005)

Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages. - Abdulkadir Utku Diril; Yuvraj Singh Dhillon; Abhijit Chatterjee; Adit D. Singh (VLSI Design, 2005)

A Delay Test to Differentiate Resistive Interconnect Faults from Weak Transistor Defects. - Haihua Yan; Adit D. Singh (VLSI Design, 2005)

Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance. - Abdulkadir Utku Diril; Yuvraj Singh Dhillon; Abhijit Chatterjee; Adit D. Singh (VTS, 2005)

Pseudo Dual Supply Voltage Domino Logic Design. - Abdulkadir Utku Diril; Yuvraj Singh Dhillon; Abhijit Chatterjee; Adit D. Singh (J. Low Power Electron., 2005)

Low Cost Launch-on-Shift Delay Test with Slow Scan Enable. - Gefu Xu; Adit D. Singh (ETS, 2006)

Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. - Maryam Ashouei; Abhijit Chatterjee; Adit D. Singh; Vivek De; T. M. Mak (VLSI Design, 2006)

Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing. - Adit D. Singh; Gefu Xu (VTS, 2006)

Combining Negative Binomial and Weibull Distributions for Yield and Reliability Prediction. - Thomas S. Barnett; Matt Grady; Kathleen G. Purdy; Adit D. Singh (IEEE Des. Test Comput., 2006)

New JETTA Editors, 2006. - Bashir M. Al-Hashimi; Dimitris Gizopoulos; Manoj Sachdev; Adit D. Singh (J. Electron. Test., 2006)

Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects. - Xiangdong Xuan; Adit D. Singh; Abhijit Chatterjee (J. Electron. Test., 2006)

Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance. - Yuvraj Singh Dhillon; Abdulkadir Utku Diril; Abhijit Chatterjee; Adit D. Singh (IEEE Trans. Very Large Scale Integr. Syst., 2006)

A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI). - Haihua Yan; Adit D. Singh (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan. - Gefu Xu; Adit D. Singh (ATS, 2007)

Achieving high transition delay fault coverage with partial DTSFF scan chains. - Gefu Xu; Adit D. Singh (ITC, 2007)

Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations. - Maryam Ashouei; Muhammad Mudassar Nisar; Abhijit Chatterjee; Adit D. Singh; Abdulkadir Utku Diril (VLSI Design, 2007)

Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing. - Gefu Xu; Adit D. Singh (VLSI Design, 2007)

Scan cell design for launch-on-shift delay tests with slow scan enable. - Gefu Xu; Adit D. Singh (IET Comput. Digit. Tech., 2007)

Scan Based Testing of Dual/Multi Core Processors for Small Delay Defects. - Adit D. Singh (ITC, 2008)

Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS. - Maryam Ashouei; Adit D. Singh; Abhijit Chatterjee (VLSI Design, 2008)

Scan Delay Testing of Nanometer SoCs. - Adit D. Singh (VLSI Design, 2008)

Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing. - K. G. Deepak; Robinson Reyna; Virendra Singh; Adit D. Singh (Asian Test Symposium, 2009)

A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS. - Adit D. Singh (DFT, 2009)

Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?. - Abhijit Chatterjee; Jacob A. Abraham; Adit D. Singh; Elie Maricau; Rakesh Kumar 002; Christos A. Papachristou (IOLTS, 2009)

Output Hazard-Free Transition Delay Fault Test Generation. - Sreekumar Menon; Adit D. Singh; Vishwani D. Agrawal (VTS, 2009)

Current Sensing Completion Detection for high speed and area efficient arithmetic. - Balapradeep Gadamsetti; Adit D. Singh (APCCAS, 2010)

Modified Scan Flip-Flop for Low Power Testing. - Amit Mishra 002; Nidhi Sinha; Satdev; Virendra Singh; Sreejit Chakravarty; Adit D. Singh (Asian Test Symposium, 2010)

Distinguishing Resistive Small Delay Defects from Random Parameter Variations. - Xi Qian; Adit D. Singh (Asian Test Symposium, 2010)

Adapting to adaptive testing. - Erik Jan Marinissen; Adit D. Singh; Dan Glotter; Marco Esposito; John M. Carulli Jr.; Amit Nahar; Kenneth M. Butler; Davide Appello; Chris Portelli (DATE, 2010)

Modified T-Flip-Flop based scan cell for RAS. - Raghavendra Adiga; Gandhi Arpit; Virendra Singh; Kewal K. Saluja; Adit D. Singh (ETS, 2010)

Test application time minimization for RAS using basis optimization of column decoder. - A. Abhishek; Amanulla Khan; Virendra Singh; Kewal K. Saluja; Adit D. Singh (ISCAS, 2010)

On Minimization of Test Application Time for RAS. - Raghavendra Adiga; Gandhi Arpit; Virendra Singh; Kewal K. Saluja; Hideo Fujiwara; Adit D. Singh (VLSI Design, 2010)

An output compression scheme for handling X-states from over-clocked delay tests. - Adit D. Singh; Chao Han; Xi Qian (VTS, 2010)

Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable Logic. - Maryam Ashouei; Abhijit Chatterjee; Adit D. Singh (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Distributed Comparison Test Driven Multiprocessor Speed-Tuning: Targeting Performance Gains under Extreme Process Variations. - Jayaram Natarajan; Joshua W. Wells; Abhijit Chatterjee; Adit D. Singh (Asian Test Symposium, 2011)

Diagnosing Multiple Slow Gates for Performance Tuning in the Face of Extreme Process Variations. - Xi Qian; Adit D. Singh; Abhijit Chatterjee (Asian Test Symposium, 2011)

SSTKR: Secure and Testable Scan Design through Test Key Randomization. - Mohammed Abdul Razzaq; Virendra Singh; Adit D. Singh (Asian Test Symposium, 2011)

Path Delay Tuning for Performance Gain in the Face of Random Manufacturing Variations. - Kautalya Mishra; Ahmed Faraz; Adit D. Singh (VLSI Design, 2011)

SEU tolerant robust memory cell design. - Mohammed Shayan; Virendra Singh; Adit D. Singh; Masahiro Fujita (IOLTS, 2012)

SEU Tolerant Robust Latch Design. - Mohammed Shayan; Virendra Singh; Adit D. Singh; Masahiro Fujita (VDAT, 2012)

Detection of gate-oxide defects with timing tests at reduced power supply. - Xi Qian; Chao Han; Adit D. Singh (VTS, 2012)

Hazard Initialized LOC Tests for TDF Undetectable CMOS Open Defects. - Chao Han; Adit D. Singh (Asian Test Symposium, 2013)

Current testing: Dead or alive? - Hans A. R. Manhaeve; Pete Harrod; Adit D. Singh; Chintan Patel; Ralf Arnolc; Davide Appello (ETS, 2013)

Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors. - Janusz Rajski; Miodrag Potkonjak; Adit D. Singh; Abhijit Chatterjee; Zain Navabi; Matthew R. Guthaus; Sezer Gören 001 (VLSI-SoC, 2013)

A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution in Completion Delays. - Ravi Tej Uppu; Ravi Kanth Uppu; Adit D. Singh; Abhijit Chatterjee (VLSI Design, 2013)

Special session 4B: Elevator talks. - Jennifer Dworak; Ronald Shawn Blanton; Masahiro Fujita; Kazumi Hatayama; Naghmeh Karimi; Michail Maniatakos; Antonis M. Paschalis; Adit D. Singh; Tian Xia (VTS, 2013)

High Resolution Pulse Propagation Driven Trojan Detection in Digital Logic: Optimization Algorithms and Infrastructure. - Sabyasachi Deyati; Barry John Muldrey; Adit D. Singh; Abhijit Chatterjee (ATS, 2014)

Timing Evaluation Tests for Scan Enable Signals with Application to TDF Testing. - Jie Zou; Chao Han; Adit D. Singh (ATS, 2014)

Detection conditions for errors in self-adaptive better-than-worst-case designs. - Ilia Polian; Jie Jiang 018; Adit D. Singh (ETS, 2014)

Error detection and recovery in better-than-worst-case timing designs. - Adit D. Singh (ETS, 2014)

On the testing of hazard activated open defects. - Chao Han; Adit D. Singh (ITC, 2014)

Timing Variation Adaptive Pipeline Design: Using Probabilistic Activity Completion Sensing with Backup Error Resilience. - Jayaram Natarajan; Sahil Kapoor; Debesh Bhatta; Abhijit Chatterjee; Adit D. Singh (VLSID, 2014)

Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths. - Ravi Kanth Uppu; Ravi Tej Uppu; Adit D. Singh; Ilia Polian (VLSID, 2014)

Improving CMOS open defect coverage using hazard activated tests. - Chao Han; Adit D. Singh (VTS, 2014)

Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware Security. - Sabyasachi Deyati; Barry John Muldrey; Adit D. Singh; Abhijit Chatterjee (ATS, 2015)

A Methodology for Identifying High Timing Variability Paths in Complex Designs. - Virendra Singh; Adit D. Singh; Kewal K. Saluja (ATS, 2015)

Scan based two-pattern tests: should they target opens instead of TDFs? - Adit D. Singh (LATS, 2015)

Embedded Tutorial ET1: Better-than-Worst-Case Timing Designs. - Adit D. Singh (VLSID, 2015)

An Efficient Transition Detector Exploiting Charge Sharing. - Yu Wang; Adit D. Singh (VLSID, 2015)

Special session: Hot topics: Statistical test methods. - Manuel J. Barragán; Gildas Léger; Florence Azaïs; Ronald D. Blanton; Adit D. Singh; Stephen Sunter (VTS, 2015)

Testing cross wire opens within complex gates. - Chao Han; Adit D. Singh (VTS, 2015)

Noise-Resilient SRAM Physically Unclonable Function Design for Security. - Sujay Pandey; Sabyasachi Deyati; Adit D. Singh; Abhijit Chatterjee (ATS, 2016)

Cell Aware and stuck-open tests. - Adit D. Singh (ETS, 2016)

Adaptive Test Methods for High IC Quality and Reliability. - Adit D. Singh (VLSID, 2016)

Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG. - Jan Burchard; Dominik Erb; Adit D. Singh; Sudhakar M. Reddy; Bernd Becker 001 (DATE, 2017)

Best paper. - Bernd Becker 001; Adit D. Singh (ETS, 2017)

Exploiting path delay test generation to develop better TDF tests for small delay defects. - Ankush Srivastava; Adit D. Singh; Virendra Singh; Kewal K. Saluja (ITC, 2017)

Identifying high variability speed-limiting paths under aging. - Ankush Srivastava; Virendra Singh; Adit D. Singh; Kewal K. Saluja (LATS, 2017)

Efficient SAT-based generation of hazard-activated TSOF tests. - Jan Burchard; Dominik Erb; Sudhakar M. Reddy; Adit D. Singh; Bernd Becker 001 (VTS, 2017)

A novel design-for-security (DFS) architecture to prevent unauthorized IC overproduction. - Ujjwal Guin; Ziqi Zhou; Adit D. Singh (VTS, 2017)

A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging. - Ankush Srivastava; Virendra Singh; Adit D. Singh; Kewal K. Saluja (J. Electron. Test., 2017)

Device aging: A reliability and security concern. - Daniel Kraak; Mottaqiallah Taouil; Said Hamdioui; Pieter Weckx; Francky Catthoor; Abhijit Chatterjee; Adit D. Singh; Hans-Joachim Wunderlich; Naghmeh Karimi (ETS, 2018)

Exploiting power supply ramp rate for calibrating cell strength in SRAM PUFs. - Wendong Wang; Adit D. Singh; Ujjwal Guin; Abhijit Chatterjee (LATS, 2018)

A Secure Low-Cost Edge Device Authentication Scheme for the Internet of Things. - Ujjwal Guin; Adit D. Singh; Mahabubul Alam; Janice Canedo; Anthony Skjellum (VLSID, 2018)

On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits. - Jan Burchard; Dominik Erb; Sudhakar M. Reddy; Adit D. Singh; Bernd Becker 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test. - Ujjwal Guin; Ziqi Zhou; Adit D. Singh (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Detecting Recycled SoCs by Exploiting Aging Induced Biases in Memory Cells. - Ujjwal Guin; Wendong Wang; Charles Harper; Adit D. Singh (HOST, 2019)

An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS Failures. - Adit D. Singh (ITC, 2019)

Two-Pattern ∆IDDQ Test for Recycled IC Detection. - Prattay Chowdhury; Ujjwal Guin; Adit D. Singh; Vishwani D. Agrawal (VLSID, 2019)

Exploring the Mysteries of System-Level Test. - Ilia Polian; Jens Anders; Steffen Becker 001; Paolo Bernardi; Krishnendu Chakrabarty; Nourhan Elhamawy; Matthias Sauer 002; Adit D. Singh; Matteo Sonza Reorda; Stefan Wagner 001 (ATS, 2020)

SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts. - Sujay Pandey; Zhiwei Liao; Shreyas Nandi; Sanya Gupta; Suriyaprakash Natarajan; Arani Sinha; Adit D. Singh; Abhijit Chatterjee (ITC, 2020)

A Zero-Cost Detection Approach for Recycled ICs using Scan Architecture. - Wendong Wang; Ujjwal Guin; Adit D. Singh (VTS, 2020)

Aging-Resilient SRAM-based True Random Number Generator for Lightweight Devices. - Wendong Wang; Ujjwal Guin; Adit D. Singh (J. Electron. Test., 2020)

Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts. - Sujay Pandey; Zhiwei Liao; Shreyas Nandi; Suriyaprakash Natarajan; Arani Sinha; Adit D. Singh; Abhijit Chatterjee (VTS, 2021)

Estimating Operational Age of an Integrated Circuit. - Prattay Chowdhury; Ujjwal Guin; Adit D. Singh; Vishwani D. Agrawal (J. Electron. Test., 2021)

High Resolution Pulse Propagation Driven Trojan Detection in Digital Systems. - Sabyasachi Deyati; Barry J. Muldrey; Adit D. Singh; Abhijit Chatterjee (J. Electron. Test., 2021)

Understanding Vmin Failures for Improved Testing of Timing Marginalities. - Adit D. Singh (ITC, 2022)

A Systematic Bit Selection Method for Robust SRAM PUFs. - Wendong Wang; Adit D. Singh; Ujjwal Guin (J. Electron. Test., 2022)

Silent Error Corruption: The New Reliability and Test Challenge. - Adit D. Singh (LATS, 2023)

Silent Data Errors: Sources, Detection, and Modeling. - Adit D. Singh; Sreejit Chakravarty; George Papadimitriou 001; Dimitris Gizopoulos (VTS, 2023)

Silent Data Corruption from Timing Marginalities Due to Process Variations. - Adit D. Singh (ETS, 2024)

Innovative Practices Track: Session 2 Silent Data Corruption. - Arani Sinha; Adit D. Singh (VTS, 2024)

Invited: Enhancing Test Quality by Targeting Timing Marginalities Due to Process Variations. - Adit D. Singh; Mukarram Ali Faridi (DAC, 2025)

Silent Data Corruption: Advancing Detection, Diagnosis, and Mitigation Strategies. - Peter Domanski; Mukarram Ali Faridi; Gabriel Kaunang; Wilson Pradeep; Adit D. Singh; Muhammad Alfian Amrizal; Yanjing Li; Farshad Firouzi; Krishnendu Chakrabarty (VTS, 2025)