HyCUBE: A CGRA with Reconfigurable Single-cycle Multi-hop Interconnect. - Manupa Karunaratne; Aditi Kulkarni Mohite; Tulika Mitra; Li-Shiuan Peh (DAC, 2017)

Dnestmap: mapping deeply-nested loops on ultra-low power CGRAs. - Manupa Karunaratne; Cheng Tan 002; Aditi Kulkarni Mohite; Tulika Mitra; Li-Shiuan Peh (DAC, 2018)

LOCUS: Low-Power Customizable Many-Core Architecture for Wearables. - Cheng Tan 002; Aditi Kulkarni Mohite; Vanchinathan Venkataramani; Manupa Karunaratne; Tulika Mitra; Li-Shiuan Peh (ACM Trans. Embed. Comput. Syst., 2018)

HyCUBE: A 0.9V 26.4 MOPS/mW, 290 pJ/op, Power Efficient Accelerator for IoT Applications. - Bo Wang 020; Manupa Karunarathne; Aditi Kulkarni Mohite; Tulika Mitra; Li-Shiuan Peh (A-SSCC, 2019)

SPECTRUM: a software defined predictable many-core architecture for LTE baseband processing. - Vanchinathan Venkataramani; Aditi Kulkarni Mohite; Tulika Mitra; Li-Shiuan Peh (LCTES, 2019)

Time-Predictable Software-Defined Architecture with Sdf-Based Compiler Flow for 5g Baseband Processing. - Vanchinathan Venkataramani; Bruno Bodin; Aditi Kulkarni Mohite; Tulika Mitra; Li-Shiuan Peh (ICASSP, 2020)

SPECTRUM: A Software-defined Predictable Many-core Architecture for LTE/5G Baseband Processing. - Vanchinathan Venkataramani; Aditi Kulkarni Mohite; Tulika Mitra; Li-Shiuan Peh (ACM Trans. Embed. Comput. Syst., 2020)

ASCENT: Communication Scheduling for SDF on Bufferless Software-Defined NoC. - Vanchinathan Venkataramani; Bruno Bodin; Aditi Kulkarni Mohite; Tulika Mitra; Li-Shiuan Peh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)