Designing Low Cost Secured DSP Core using Steganography and PSO for CE systems. - Aditya Anshul; K. Bharath; Anirban Sengupta (iSES, 2022)

IP Core Protection of Image Processing Filters with Multi-Level Encryption and Covert Steganographic Security Constraints. - Aditya Anshul; Anirban Sengupta (iSES, 2022)

Palmprint Biometric Versus Encrypted Hash Based Digital Signature for Securing DSP Cores Used in CE Systems. - Rahul Chaurasia; Aditya Anshul; Anirban Sengupta; Shikha Gupta (IEEE Consumer Electron. Mag., 2022)

Hardware Security of Digital Image Filter IP Cores against Piracy using IP Seller's Fingerprint Encrypted Amino Acid Biometric Sample. - Anirban Sengupta; Rahul Chaurasia; Aditya Anshul (AsianHOST, 2023)

Secured and Optimized Hardware Accelerators using Key-Controlled Encoded Hash Slices and Firefly Algorithm based Exploration. - Anirban Sengupta; Aditya Anshul; Chirag Kothari; Sumer Thakur (ICM, 2023)

Fusing IP vendor Palmprint Biometric with Encoded Hash for Hardware IP Core Protection of Image Processing Filters. - Anirban Sengupta; Aditya Anshul; Sumer Thakur; Chirag Kothari (ICM, 2023)

Low-Cost Hardware Security of Laplace Edge Detection and Embossment Filter Using HLS Based Encryption and PSO. - Aditya Anshul; Anirban Sengupta (iSES, 2023)

Key-Driven Multi-Layered Structural Obfuscation of IP cores using Reconfigurable Obfuscator based Network Challenge and Switch Control Logic. - Anirban Sengupta; Aditya Anshul (iSES, 2023)

Exploration of optimal crypto-chain signature embedded secure JPEG-CODEC hardware IP during high level synthesis. - Aditya Anshul; Anirban Sengupta (Microprocess. Microsystems, 2023)

Exploration of optimal functional Trojan-resistant hardware intellectual property (IP) core designs during high level synthesis. - Anirban Sengupta; Aditya Anshul; Rahul Chaurasia (Microprocess. Microsystems, 2023)

Exploring Handwritten Signature Image Features for Hardware Security. - Mahendra Rathor; Anirban Sengupta; Rahul Chaurasia; Aditya Anshul (IEEE Trans. Dependable Secur. Comput., 2023)

Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores. - Mahendra Rathor; Aditya Anshul; K. Bharath; Rahul Chaurasia; Anirban Sengupta (Comput. Electr. Eng., 2023)

Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key. - Anirban Sengupta; Rahul Chaurasia; Aditya Anshul (IEEE Trans. Very Large Scale Integr. Syst., 2023)

PSO based exploration of multi-phase encryption based secured image processing filter hardware IP core datapath during high level synthesis. - Aditya Anshul; Anirban Sengupta (Expert Syst. Appl., 2023)

HLS Scheduling Driven Encoded Watermarking for Secure Convolutional Layer IP Design in CNN. - Anirban Sengupta; Vishal Chourasia; Aditya Anshul (ICCE-Taiwan, 2024)

Robust Watermarking of Loop Unrolled Convolution Layer IP Design for CNN using 4-variable Encoded Register Allocation. - Anirban Sengupta; Vishal Chourasia; Aditya Anshul; Nitish Kumar (ICCE-Taiwan, 2024)

HLS Based Hardware Watermarking Using IP Seller's Superimposed Facial Anthropometric Features. - Anirban Sengupta; Aditya Anshul; Vishal Chourasia (iSES, 2024)

Watermarking Hardware IPs Using Design Parameter Driven Encrypted Dispersion Matrix With Eigen Decomposition Based Security Framework. - Anirban Sengupta; Aditya Anshul (IEEE Access, 2024)

Securing Reusable IP Cores Using Voice Biometric Based Watermark. - Mahendra Rathor; Aditya Anshul; Anirban Sengupta (IEEE Trans. Dependable Secur. Comput., 2024)

Hardware Security of Image Processing Cores Against IP Piracy Using PSO-Based HLS-Driven Multi-Stage Encryption Fused with Fingerprint Signature. - Anirban Sengupta; Aditya Anshul (SN Comput. Sci., 2024)

A Survey of High-Level Synthesis-Based Hardware (IP) Watermarking Approaches. - Anirban Sengupta; Aditya Anshul (IEEE Des. Test, 2024)

M-HLS: Malevolent High-Level Synthesis for Watermarked Hardware IPs. - Anirban Sengupta; Aditya Anshul; Vishal Chourasia; Nitish Kumar (IEEE Embed. Syst. Lett., 2024)

Security Vulnerability (Backdoor Trojan) During Machine Learning Accelerator Design Phases. - Anirban Sengupta; Aditya Anshul; Vishal Chourasia; Nabendu Bhui (IT Prof., 2025)

Hardware security against IP piracy using secure fingerprint encrypted fused amino-acid biometric with facial anthropometric signature. - Anirban Sengupta; Aditya Anshul; Ayush Kumar Singh (Microprocess. Microsystems, 2025)