Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction. - Aditya Japa; Harshita Vallabhaneni; Ramesh Vaddi (IET Circuits Devices Syst., 2016)

Tunneling Field Effect Transistors for Energy Efficient Logic, Sensor Interface and 3D IC Circuits for IoT Platforms. - Aditya Japa; T. Nagateja; Ramesh Vaddi (iNIS, 2017)

Exploiting Characteristics of Steep Slope Tunnel Transistors Towards Energy Efficient and Reliable Buffer Designs for IoT SoCs. - Aditya Japa; Harshita Vallabhaneni; Ramesh Vaddi (VDAT, 2017)

Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities. - Aditya Japa; T. Nagateja; Santosh Kumar Vishvakarma; Yellappa Palagani; Jun Rim Choi; Ramesh Vaddi (ISCAS, 2018)

Tunnel FET ambipolarity-based energy efficient and robust true random number generator against reverse engineering attacks. - Aditya Japa; Manoj Kumar Majumder; Subhendu Kumar Sahoo; Ramesh Vaddi (IET Circuits Devices Syst., 2019)

A Low Voltage Discriminant Circuit for Pattern Recognition Exploiting the Asymmetrical Characteristics of Tunnel FET. - Aditya Japa; Yellappa Palagani; Venkateswarlu Gonuguntla; Manoj Kumar Majumder; Subhendu Kumar Sahoo; Jun Rim Choi; Ramesh Vaddi (ISCAS, 2020)

Low area overhead DPA countermeasure exploiting tunnel transistor-based random number generator. - Aditya Japa; Manoj Kumar Majumder; Subhendu Kumar Sahoo; Ramesh Vaddi (IET Circuits Devices Syst., 2020)

Tunnel FET-based ultralow-power and hardware-secure circuit design considering p-i-n forward leakage. - Aditya Japa; Manoj Kumar Majumder; Subhendu Kumar Sahoo; Ramesh Vaddi (Int. J. Circuit Theory Appl., 2020)

Steep Switching NCFET based Logic for Future Energy Efficient Electronics. - Renuka Chowdary Bheemana; Aditya Japa; Siva Sankar Yellampalli; Ramesh Vaddi (iSES, 2021)

Tunnel FET-based ultra-lightweight reconfigurable TRNG and PUF design for resource-constrained internet of things. - Aditya Japa; Manoj Kumar Majumder; Subhendu Kumar Sahoo; Ramesh Vaddi (Int. J. Circuit Theory Appl., 2021)

A Reconfigurable Arbiter PUF Based on VGSOT MTJ. - Kunal Kranti Das; Aditya Japa; Deepika Gupta (VDAT, 2022)

Negative capacitance FETs for energy efficient and hardware secure logic designs. - Renuka Chowdary Bheemana; Aditya Japa; Siva Sankar Yellampalli; Ramesh Vaddi (Microelectron. J., 2022)

Processor based Intrinsic PUF Design for Approximate Computing: Faith or Reality? - Aditya Japa; Jiliang Zhang 002; Weiqiang Liu 001; Chongyan Gu (AsianHOST, 2023)

Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design. - Renuka Chowdary Bheemana; Aditya Japa; Siva Sankar Yellampalli; Ramesh Vaddi (Microelectron. J., 2023)

Negative Capacitance FET 8T SRAM Computing in-Memory based Logic Design for Energy Efficient AI Edge Devices. - Venu Birudu; Tirumalarao Kadiyam; Koteswararao Penumalli; Aditya Japa; Sushma Nirmala Sambatur; Chongyan Gu; Siva Sankar Yellampalli; Ramesh Vaddi (ISCAS, 2024)

A Novel Methodology for Processor based PUF in Approximate Computing. - Aditya Japa; Jack Miskelly; Yijun Cui; Máire O'Neill; Chongyan Gu (ISCAS, 2024)