VLSI design of APT-VDF using novel variable block sized ternary adder and multiplier. - Aditya Mandloi; Santosh Pawar (Microprocess. Microsystems, 2020)

Power and delay efficient fir filter design using ESSA and VL-CSKA based booth multiplier. - Aditya Mandloi; Santosh Pawar (Microprocess. Microsystems, 2021)