Analysis and solutions to issue queue process variation. - Niranjan Soundararajan; Aditya Yanamandra; Chrysostomos Nicopoulos; Narayanan Vijaykrishnan; Anand Sivasubramaniam; Mary Jane Irwin (DSN, 2008)

A low-power phase change memory based hybrid cache architecture. - Prasanth Mangalagiri; Karthik Sarpatwari; Aditya Yanamandra; Vijaykrishnan Narayanan; Yuan Xie 001; Mary Jane Irwin; Osama Awadel Karim (ACM Great Lakes Symposium on VLSI, 2008)

Evaluating the role of scratchpad memories in chip multiprocessors for sparse matrix computations. - Aditya Yanamandra; Bryan Cover; Padma Raghavan; Mary Jane Irwin; Mahmut T. Kandemir (IPDPS, 2008)

In-Network Caching for Chip Multiprocessors. - Aditya Yanamandra; Mary Jane Irwin; Vijaykrishnan Narayanan; Mahmut T. Kandemir; Sri Hari Krishna Narayanan (HiPEAC, 2009)

Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network. - Yuan Xie 001; Soumya Eachempati; Aditya Yanamandra; Vijaykrishnan Narayanan; Mary Jane Irwin (NANOARCH, 2009)

Optimizing power and performance for reliable on-chip networks. - Aditya Yanamandra; Soumya Eachempati; Niranjan Soundararajan; Vijaykrishnan Narayanan; Mary Jane Irwin; Ramakrishnan Krishnan (ASP-DAC, 2010)

On the Effects of Process Variation in Network-on-Chip Architectures. - Chrysostomos Nicopoulos; Suresh Srinivasan; Aditya Yanamandra; Dongkook Park; Vijaykrishnan Narayanan; Chita R. Das; Mary Jane Irwin (IEEE Trans. Dependable Secur. Comput., 2010)

RAFT: A router architecture with frequency tuning for on-chip networks. - Asit K. Mishra; Aditya Yanamandra; Reetuparna Das; Soumya Eachempati; Ravi R. Iyer 001; Narayanan Vijaykrishnan; Chita R. Das (J. Parallel Distributed Comput., 2011)