A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements. - Harold Pilo; Igor Arsovski; Kevin Batson; Geordie Braceras; John A. Gabric; Robert M. Houle; Steve Lamphier; Frank Pavlik; Adnan Seferagic; Liang-Yu Chen; Shang-Bin Ko; Carl Radens (ISSCC, 2011)

A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements. - Harold Pilo; Igor Arsovski; Kevin Batson; Geordie Braceras; John A. Gabric; Robert M. Houle; Steve Lamphier; Carl Radens; Adnan Seferagic (IEEE J. Solid State Circuits, 2012)

A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction. - Harold Pilo; Chad A. Adams; Igor Arsovski; Robert M. Houle; Steve Lamphier; Michael M. Lee; Frank Pavlik; Sushma N. Sambatur; Adnan Seferagic; Richard Wu; Mohammad Imran Younus (ISSCC, 2013)