Analysis of Bounded Linear Cellular Automata Based on a Method of Image Charges. - Howard C. Card; Adonios Thanailakis; Werner Pries; Robert D. McLeod (J. Comput. Syst. Sci., 1986)

Group Properties of Cellular Automata and VLSI Applications. - Werner Pries; Adonios Thanailakis; Howard C. Card (IEEE Trans. Computers, 1986)

Algebraic Theory of Bounded One-dimensional Cellular Automata. - Nikos Pitsianis; Georgios L. Bleris; Philippos Tsalides; Adonios Thanailakis; Howard C. Card (Complex Syst., 1989)

Synchronization of D. Parkinsonasynchronous concurrent processes using cellular automata. - E. D. Adamides; Philippos Tsalides; Adonios Thanailakis (Parallel Comput., 1989)

Hierarchical Cellular Graph Automata as a Novel Architecture for Computer-Supported Cooperative Work. - Emmanuel D. Adamides; Philippos Tsalides; Adonios Thanailakis (Comput. J., 1992)

Two-Dimensional Cellular Automata: Properties and Applications of a New VLSI Architecture. - Philippos Tsalides; Adonios Thanailakis; Nikos Pitsianis; Georgios L. Bleris (Comput. J., 1992)

Hierarchical Cellular Automata structures. - E. D. Adamides; Philippos Tsalides; Adonios Thanailakis (Parallel Comput., 1992)

2-Dimensional minimum cost path planning using a cellular automaton architecture. - Panagiotis Tzionas; Philippos Tsalides; Antonios Thanailakis (Integr., 1993)

Bit-serial VLSI sorter with high reliability specifications. - E. D. Adamides; Philippos G. Tsalides; Adonios Thanailakis (Microprocess. Microprogramming, 1994)

A modified discrete Fourier-cosine transform algorithm and its VLSI implementation. - Panagiotis Tzionas; Philippos Tsalides; Adonios Thanailakis (Microprocess. Microsystems, 1994)

A new, cellular automaton-based, nearest neighbor pattern classifier and its VLSI implementation. - Panagiotis Tzionas; Philippos G. Tsalides; Adonios Thanailakis (IEEE Trans. Very Large Scale Integr. Syst., 1994)

A Parallel Skeletonization Algorithm Based on Two-Dimensional Cellular Automata and its VLSI Implementation. - Panagiotis Tzionas; Philippos G. Tsalides; Adonios Thanailakis (Real Time Imaging, 1995)

Low-power design of array architectures. - Dimitrios Soudris; George Theodoridis; S. Theoharis; Adonios Thanailakis (ICECS, 1996)

A hybrid cellular automaton/neural network classifier for multi-valued patterns and its VLSI implementation. - Panagiotis Tzionas; Antonios Thanailakis; Philippos Tsalides (Integr., 1996)

A new hardware module for automated visual inspection based on a cellular automaton architecture. - Ioannis Andreadis; Ioannis Karafyllidis; Panagiotis Tzionas; Adonios Thanailakis; Philippos Tsalides (J. Intell. Robotic Syst., 1996)

A cellular automaton for the determination of the mean velocity of moving objects and its VLSI implementation. - Ioannis Karafyllidis; Ioannis Andreadis; Panagiotis Tzionas; Philippos G. Tsalides; Adonios Thanailakis (Pattern Recognit., 1996)

An efficient algorithm for the largest empty figure problem based on a 2D cellular automaton architecture. - Panagiotis Tzionas; Adonios Thanailakis; Philippos G. Tsalides (Image Vis. Comput., 1997)

Geometrical Shape Recognition Using a Cellular Automaton Architecture and its VLSI Implementation. - Ioannis Karafyllidis; A. Ioannidis; Adonios Thanailakis; Philippos Tsalides (Real Time Imaging, 1997)

Collision-free path planning for a diamond-shaped robot using two-dimensional cellular automata. - Panagiotis Tzionas; Adonios Thanailakis; Philippos G. Tsalides (IEEE Trans. Robotics Autom., 1997)

Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic. - I. Thoidis; Dimitrios Soudris; Ioannis Karafyllidis; Adonios Thanailakis; Thanos Stouraitis (Great Lakes Symposium on VLSI, 1998)

Non-linear Hybrid Cellular Automata as Pseudorandom Pattern Generators for VLSI Systems. - Ioannis Karafyllidis; Ioannis Andreadis; Philippos G. Tsalides; Adonios Thanailakis (VLSI Design, 1998)

Estimation of power dissipation in glitching using complex-time cellular automata. - Ioannis Karafyllidis; Stelios Mavridis; Dimitrios Soudris; Adonios Thanailakis (ICECS, 1999)

A new adiabatic technique for designing low power array architectures. - C. Z. Lolas; Dimitrios Soudris; Ioannis Karafyllidis; Adonios Thanailakis (ICECS, 1999)

Genetic partitioning and placement for VLSI circuits. - George Ch. Sirakoulis; Ioannis Karafyllidis; Adonios Thanailakis (ICECS, 1999)

The design of low power multiple-valued logic encoder and decoder circuits. - I. Thoidis; D. J. Soudris; Ioannis Karafyllidis; Adonios Thanailakis (ICECS, 1999)

The VLSI implementation of a baseband receiver for DECT-based portable applications. - M. Perakis; A. E. Tzimas; E. G. Metaxakis; Dimitrios Soudris; Grigorios A. Kalivas; C. Katis; Chrissavgi Dre; Constantinos E. Goutis; Adonios Thanailakis; Thanos Stouraitis (ISCAS (1), 1999)

Designing RNS and QRNS full adder based converters. - D. J. Soudris; Minas Dasygenis; Adonios Thanailakis (ISCAS, 2000)

Low power design of a multi-mode transceiver. - Dimitrios Soudris; Minas Perakis; Haris Mizas; Vasilios A. Mardiris; Kosfas Katis; Chrissavgi Dre; A. E. Tzimas; E. G. Metaxakis; Grigorios Kalivas; Nikolaos D. Zervas; Spyros Theoharis; George Theodoridis; et al. (ISCAS, 2000)

A methodology for the behavioral-level event-driven power management of digital receivers. - Nikolaos D. Zervas; Dimitrios Soudris; Spyros Theoharis; Constantinos E. Goutis; Adonios Thanailakis (ISCAS, 2000)

Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications. - Dimitrios Soudris; Nikolaos D. Zervas; Antonios Argyriou; Minas Dasygenis; Konstantinos Tatas; Constantinos E. Goutis; Adonios Thanailakis (PATMOS, 2000)

Designing low-power energy recovery adders based on pass transistor logic. - Dimitrios Soudris; Vasilis F. Pavlidis; Adonios Thanailakis (ICECS, 2001)

Power, performance and area exploration of block matching algorithms mapped on programmable processors. - Nikolas Kroupis; Minas Dasygenis; Antonios Argyriou; Konstantinos Tatas; Dimitrios Soudris; Antonios Thanailakis; Nikolaos D. Zervas; Constantinos E. Goutis (ICIP (3), 2001)

A CAD tool for architecture level exploration and automatic generation of RNS converters. - D. J. Soudris; Minas Dasygenis; Spyridoula K. Vasilopoulou; Adonios Thanailakis (ISCAS (4), 2001)

The circuit design of multiple-valued logic voltage-mode adders. - Ioannis M. Thoidis; Dimitrios Soudris; Jean-Marc Fernandez; Adonios Thanailakis (ISCAS (4), 2001)

Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. - George Koutroumpezis; Konstantinos Tatas; Dimitrios Soudris; Spyros Blionas; Kostas Masselos; Adonios Thanailakis (FPL, 2002)

A full adder based methodology for scaling operation in residue number system. - Dimitrios Soudris; Minas Dasygenis; K. Mitroglou; Konstantinos Tatas; Adonios Thanailakis (ICECS, 2002)

A novel division algorithm for parallel and sequential processing. - Konstantinos Tatas; D. J. Soudris; D. Siomos; Minas Dasygenis; Adonios Thanailakis (ICECS, 2002)

A cellular automaton methodology for the simulation of integrated circuit fabrication processes. - Georgios Ch. Sirakoulis; Ioannis Karafyllidis; Adonios Thanailakis (Future Gener. Comput. Syst., 2002)

A fast and accurate delay dependent method for switching estimation of large combinational circuits. - S. Theoharis; George Theodoridis; Dimitrios Soudris; Constantinos E. Goutis; Adonios Thanailakis (J. Syst. Archit., 2002)

Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms. - Konstantinos Tatas; Kostas Siozios; Dimitrios Soudris; Adonios Thanailakis (FPL, 2003)

Alternative Direct Digital Frequency Synthesizer architectures with reduced memory size. - Dimitrios Soudris; Marios Kesoulis; Christos S. Koukourlis; Adonios Thanailakis; Spyros Blionas (ISCAS (2), 2003)

A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems. - Dimitrios Soudris; K. Sgouropoulos; Konstantinos Tatas; Vasilis F. Pavlidis; Adonios Thanailakis (ISCAS (5), 2003)

Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms. - Konstantinos Tatas; Kostas Siozios; Dimitrios Soudris; Adonios Thanailakis; Kostas Masselos; Konstantinos Potamianos; Spyros Blionas (PATMOS, 2003)

FPGA Architecture Design and Toolset for Logic Implementation. - Konstantinos Tatas; Kostas Siozios; Nikolaos Vassiliadis; D. J. Soudris; Spiridon Nikolaidis 001; Stilianos Siskos; Adonios Thanailakis (PATMOS, 2003)

Designing Low Power Direct Digital Frequency Synthesizers. - Marios Kesoulis; Dimitrios Soudris; Christos S. Koukourlis; Adonios Thanailakis (VLSI-SOC, 2003)

A cellular automaton model for the study of DNA sequence evolution. - Georgios Ch. Sirakoulis; Ioannis Karafyllidis; Ch. Mizas; Vasilios A. Mardiris; Adonios Thanailakis; Philippos Tsalides (Comput. Biol. Medicine, 2003)

A CAD system for the construction and VLSI implementation of Cellular Automata algorithms using VHDL. - Georgios Ch. Sirakoulis; Ioannis Karafyllidis; Adonios Thanailakis (Microprocess. Microsystems, 2003)

Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms. - Konstantinos Tatas; Minas Dasygenis; Nikolas Kroupis; Antonios Argyriou; Dimitrios Soudris; Antonios Thanailakis (Real Time Imaging, 2003)

A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development. - Kostas Siozios; George Koutroumpezis; Konstantinos Tatas; Dimitrios Soudris; Adonios Thanailakis (FPL, 2004)

An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development. - Vasilios Kalenteridis; Haroula Pournara; Kostas Siozios; Konstantinos Tatas; George Koutroumpezis; Ilias Pappas 001; Spiridon Nikolaidis 001; Stilianos Siskos; D. J. Soudris; Adonios Thanailakis (IPDPS, 2004)

A reusable IP FFT core for DSP applications. - Evaggelia Theochari; Konstantinos Tatas; Dimitrios Soudris; Kostas Masselos; Konstantinos Potamianos; Spyros Blionas; Antonios Thanailakis (ISCAS (3), 2004)

Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications. - Minas Dasygenis; Erik Brockmeyer; Bart Durinck; Francky Catthoor; Dimitrios Soudris; Antonios Thanailakis (SAMOS, 2004)

Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology. - Stylianos Mamagkakis; Alexandros Mpartzas; Georgios Pouiklis; David Atienza; Francky Catthoor; Dimitrios Soudris; Jose Manuel Mendias; Antonios Thanailakis (WWIC, 2004)

Design and simulation of a nanoelectronic single-electron universal Control-Control-Not gate. - Ioannis Tsimperidis; Ioannis Karafyllidis; Antonios Thanailakis (Microelectron. J., 2004)

AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow. - Dimitrios Soudris; Spiridon Nikolaidis 001; Stilianos Siskos; Konstantinos Tatas; Kostas Siozios; George Koutroumpezis; Nikolaos Vassiliadis; Vasilios Kalenteridis; Haroula Pournara; Ilias Pappas 001; Adonios Thanailakis (ASP-DAC, 2005)

A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck. - Minas Dasygenis; Erik Brockmeyer; Bart Durinck; Francky Catthoor; Dimitrios Soudris; Antonios Thanailakis (DATE, 2005)

A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow. - Kostas Siozios; Dimitrios Soudris; Adonios Thanailakis (FPL, 2005)

An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform. - Kostas Siozios; Konstantinos Tatas; George Koutroumpezis; D. J. Soudris; Adonios Thanailakis (FPL, 2005)

DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation. - Kostas Siozios; George Koutroumpezis; Konstantinos Tatas; Dimitrios Soudris; Adonios Thanailakis (IPDPS, 2005)

A modified spiral search motion estimation algorithm and its embedded system implementation. - Nikolas Kroupis; Minas Dasygenis; Kleoniki Markou; Dimitrios Soudris; Adonios Thanailakis (ISCAS (4), 2005)

Improving the Memory Bandwidth Utilization Using Loop Transformations. - Minas Dasygenis; Erik Brockmeyer; Francky Catthoor; Dimitrios Soudris; Antonios Thanailakis (PATMOS, 2005)

A Modified Spiral Search Algorithm and its Embedded Hardware Implementation. - Nikolas Kroupis; Minas Dasygenis; Dimitrios Soudris; Antonios Thanailakis (IEC (Prague), 2005)

Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications. - Stylianos Mamagkakis; Christos Baloukas; David Atienza; Francky Catthoor; Dimitrios Soudris; José M. Mendías; Antonios Thanailakis (WWIC, 2005)

A fault-tolerant message passing algorithm and its hardware implementation. - Georgios Ch. Sirakoulis; V. Raptis; Ioannis Karafyllidis; Philippos Tsalides; Adonios Thanailakis (Adv. Eng. Softw., 2005)

A cellular automaton for the propagation of circular fronts and its applications. - Georgios Ch. Sirakoulis; Ioannis Karafyllidis; Adonios Thanailakis (Eng. Appl. Artif. Intell., 2005)

A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications. - Kostas Siozios; George Koutroumpezis; Konstantinos Tatas; Nikolaos Vassiliadis; Vasilios Kalenteridis; Haroula Pournara; Ilias Pappas 001; Dimitrios Soudris; Antonios Thanailakis; Spiridon Nikolaidis 001; Stilianos Siskos (IEICE Trans. Inf. Syst., 2005)

A Novel Division Algorithm and Architectures for Parallel and Sequential Processing. - Konstantinos Tatas; Dimitrios Soudris; D. Siomos; Adonios Thanailakis (J. Circuits Syst. Comput., 2005)

Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms. - Konstantinos Tatas; Dimitrios Soudris; Adonios Thanailakis (J. Embed. Comput., 2005)

Substrate current and degradation of n-channel polycrystalline silicon thin-film transistors. - N. A. Hastas; N. Archontas; C. A. Dimitriadis; G. Kamarinos; T. Nikolaidis; N. Georgoulas; Adonios Thanailakis (Microelectron. Reliab., 2005)

Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications. - Alexandros Bartzas; Stylianos Mamagkakis; Georgios Pouiklis; David Atienza; Francky Catthoor; Dimitrios Soudris; Antonios Thanailakis (DATE, 2006)

A novel methodology for designing high-performance and low-energy FPGA routing architecture. - Kostas Siozios; Konstantinos Tatas; Dimitrios Soudris; Antonios Thanailakis (FPGA, 2006)

Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications. - Kostas Siozios; Konstantinos Tatas; Dimitrios Soudris; Adonios Thanailakis (IPDPS, 2006)

A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications. - Kostas Siozios; Dimitrios Soudris; Adonios Thanailakis (ISCAS, 2006)

Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources. - Kostas Siozios; Dimitrios Soudris; Antonios Thanailakis (PATMOS, 2006)

Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique. - Kostas Siozios; Dimitrios Soudris; Antonios Thanailakis (VLSI-SoC, 2006)

Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance. - Stylianos Mamagkakis; Christos Baloukas; David Atienza; Francky Catthoor; Dimitrios Soudris; Antonios Thanailakis (Comput. Commun., 2006)

A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck. - Minas Dasygenis; Erik Brockmeyer; Bart Durinck; Francky Catthoor; Dimitrios Soudris; Adonios Thanailakis (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors. - Nikolas Kroupis; Nikolaos D. Zervas; Minas Dasygenis; Konstantinos Tatas; Antonios Argyriou; Dimitrios Soudris; Antonios Thanailakis (J. VLSI Signal Process., 2006)

Designing Heterogeneous FPGAs with Multiple SBs. - Kostas Siozios; Stelios Mamagkakis; Dimitrios Soudris; Antonios Thanailakis (ARC, 2007)

Systematic methodology for designing low power direct digital frequency synthesisers. - Marios Kesoulis; Dimitrios Soudris; Christos S. Koukourlis; Adonios Thanailakis (IET Circuits Devices Syst., 2007)

Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications. - Konstantinos Tatas; George Koutroumpezis; Dimitrios Soudris; Adonios Thanailakis (Integr., 2007)

Systematic methodology for exploration of performance - Energy trade-offs in network applications using Dynamic Data Type refinement. - Stylianos Mamagkakis; Alexandros Bartzas; Georgios Pouiklis; David Atienza; Francky Catthoor; Dimitrios Soudris; Antonios Thanailakis (J. Syst. Archit., 2007)

Designing a General-Purpose Interconnection Architecture for Field Programmable Gate Arrays. - Kostas Siozios; Dimitrios Soudris; Antonios Thanailakis (J. Low Power Electron., 2008)

A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System. - Minas Dasygenis; K. Mitroglou; Dimitrios Soudris; Adonios Thanailakis (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A CAD System for Modeling and Simulation of Computer Networks Using Cellular Automata. - Vasilios A. Mardiris; Georgios Ch. Sirakoulis; Ch. Mizas; Ioannis Karafyllidis; Adonios Thanailakis (IEEE Trans. Syst. Man Cybern. Part C, 2008)

A Novel Allocation Methodology for Partial and Dynamic Bitstream Generation for FPGA Architectures. - Kostas Siozios; Dimitrios Soudris; Antonios Thanailakis (J. Circuits Syst. Comput., 2010)