EazyHTM: eager-lazy hardware transactional memory. - Sasa Tomic; Cristian Perfumo; Chinmay Eishan Kulkarni; Adrià Armejach; Adrián Cristal; Osman S. Unsal; Tim Harris 001; Mateo Valero (MICRO, 2009)

Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory. - Adrià Armejach; Azam Seyedi; J. Rubén Titos Gil; Ibrahim Hur; Adrián Cristal; Osman S. Unsal; Mateo Valero (PACT, 2011)

Circuit design of a dual-versioning L1 data cache for optimistic concurrency. - Azam Seyedi; Adrià Armejach; Adrián Cristal; Osman S. Unsal; Ibrahim Hur; Mateo Valero (ACM Great Lakes Symposium on VLSI, 2011)

Transactional prefetching: narrowing the window of contention in hardware transactional memory. - Anurag Negi; Adrià Armejach; Adrián Cristal; Osman S. Unsal; Per Stenström (PACT, 2012)

Novel SRAM bias control circuits for a low power L1 data cache. - Azam Seyedi; Adrià Armejach; Adrián Cristal; Osman S. Unsal; Mateo Valero (NORCHIP, 2012)

Circuit design of a dual-versioning L1 data cache. - Azam Seyedi; Adrià Armejach; Adrián Cristal; Osman S. Unsal; Ibrahim Hur; Mateo Valero (Integr., 2012)

HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory. - Adrià Armejach; Anurag Negi; Adrián Cristal; Osman S. Unsal; Per Stenström; Tim Harris 001 (HiPC, 2013)

Techniques to improve performance in requester-wins hardware transactional memory. - Adrià Armejach; J. Rubén Titos Gil; Anurag Negi; Osman S. Unsal; Adrián Cristal (ACM Trans. Archit. Code Optim., 2013)

An empirical evaluation of High-Level Synthesis languages and tools for database acceleration. - Oriol Arcas-Abella; Geoffrey Ndu; Nehir Sönmez; Mohsen Ghasempour; Adrià Armejach; Javier Navaridas; Wei Song 002; John Mawer; Adrián Cristal; Mikel Luján (FPL, 2014)

Techniques to improve concurrency in hardware transactional memory. - Adrià Armejach (2014)

Tidy Cache: Improving Data Placement in Die-Stacked DRAM Caches. - Adrià Armejach; Adrián Cristal; Osman S. Unsal (SBAC-PAD, 2015)

Implications of non-volatile memory as primary storage for database management systems. - Naveed Ul Mustafa; Adrià Armejach; Özcan Özturk 001; Adrián Cristal; Osman S. Unsal (SAMOS, 2016)

MUSA: a multi-level simulation approach for next-generation HPC machines. - Thomas Grass; César Allande; Adrià Armejach; Alejandro Rico; Eduard Ayguadé; Jesús Labarta; Mateo Valero; Marc Casas; Miquel Moretó (SC, 2016)

Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs, and Memory. - Oriol Arcas-Abella; Adrià Armejach; Timothy Hayes 001; Gorker Alp Malazgirt; Oscar Palomar; Behzad Salami 001; Nehir Sönmez (Comput. Sci. Eng., 2016)

Stencil codes on a vector length agnostic architecture. - Adrià Armejach; Helena Caminal; Juan M. Cebrian; Rekai González-Alberquilla; Chris Adeniyi-Jones; Mateo Valero; Marc Casas; Miquel Moretó (PACT, 2018)

Design Space Exploration of Next-Generation HPC Machines. - Constantino Gómez; Francesc Martínez; Adrià Armejach; Miquel Moretó; Filippo Mantovani; Marc Casas (IPDPS, 2019)

Design trade-offs for emerging HPC processors based on mobile market technology. - Adrià Armejach; Marc Casas; Miquel Moretó (J. Supercomput., 2019)

Evaluating Mixed-Precision Arithmetic for 3D Generative Adversarial Networks to Simulate High Energy Physics Detectors. - John Osorio Ríos; Adrià Armejach; Gulrukh Khattak; Eric Petit 002; Sofia Vallecorsa; Marc Casas (ICMLA, 2020)

The gem5 Simulator: Version 20.0+. - Jason Lowe-Power; Abdul Mutaal Ahmad; Ayaz Akram; Mohammad Alian; Rico Amslinger; Matteo Andreozzi; Adrià Armejach; Nils Asmussen; Srikant Bharadwaj; Gabe Black; Gedare Bloom; Bobby R. Bruce; et al. (CoRR, 2020)

Using Arm's scalable vector extension on stencil codes. - Adrià Armejach; Helena Caminal; Juan M. Cebrian; Rubén Langarita; Rekai González-Alberquilla; Chris Adeniyi-Jones; Mateo Valero; Marc Casas; Miquel Moretó (J. Supercomput., 2020)

Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors. - Adrià Armejach; Bine Brank; Jordi Cortina; François Dolique; Timothy Hayes 001; Nam Ho; Pierre-Axel Lagadec; Romain Lemaire; Guillem López-Paradís; Laurent Marliac; Miquel Moretó; Pedro Marcuello; et al. (DATE, 2021)

Dynamically Adapting Floating-Point Precision to Accelerate Deep Neural Network Training. - John Osorio Ríos; Adrià Armejach; Eric Petit 002; Greg Henry; Marc Casas (ICMLA, 2021)

gem5 + rtl: A Framework to Enable RTL Models Inside a Full-System Simulator. - Guillem López-Paradís; Adrià Armejach; Miquel Moretó (ICPP, 2021)

PLANAR: a programmable accelerator for near-memory data rearrangement. - Adrián Barredo; Adrià Armejach; Jonathan C. Beard; Miquel Moretó (ICS, 2021)

Multilevel simulation-based co-design of next generation HPC microprocessors. - Lilia Zaourar; Mohamed Benazouz; Ayoub Mouhagir; Fatma Jebali; Tanguy Sassolas; Jean-Christophe Weill; Carlos Falquez; Nam Ho; Dirk Pleiter; Antoni Portero; Estela Suarez; Polydoros Petrakis; et al. (PMBS, 2021)

On the use of many-core Marvell ThunderX2 processor for HPC workloads. - Víctor Soria Pardos; Adrià Armejach; Darío Suárez Gracia; Miquel Moretó (J. Supercomput., 2021)

FASE: A Fast, Accurate and Seamless Emulator for Custom Numerical Formats. - John Osorio Ríos; Adrià Armejach; Eric Petit 002; Greg Henry; Marc Casas (ECML/PKDD (5), 2022)

Compressed Sparse FM-Index: Fast Sequence Alignment Using Large K-Steps. - Rubén Langarita; Adrià Armejach; Javier Setoain; Pablo Ibáñez-Marín; Jesús Alastruey-Benedé; Miquel Moretó (IEEE ACM Trans. Comput. Biol. Bioinform., 2022)

A BF16 FMA is All You Need for DNN Training. - John Osorio Ríos; Adrià Armejach; Eric Petit 002; Greg Henry; Marc Casas (IEEE Trans. Emerg. Top. Comput., 2022)

Fast Behavioural RTL Simulation of 10B Transistor SoC Designs with Metro-Mpi. - Guillem López-Paradís; Brian Li; Adrià Armejach; Stefan Wallentowitz; Miquel Moretó; Jonathan Balkind (DATE, 2023)

DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations. - Víctor Soria Pardos; Adrià Armejach; Tiago Mück; Darío Suárez Gracia; José A. Joao; Alejandro Rico; Miquel Moretó (ISCA, 2023)

A Tensor Marshaling Unit for Sparse Tensor Algebra on General-Purpose Processors. - Marco Siracusa; Víctor Soria Pardos; Francesco Sgherzi; Joshua Randall 001; Douglas J. Joseph; Miquel Moretó Planas; Adrià Armejach (MICRO, 2023)

Efficient Direct Convolution Using Long SIMD Instructions. - Alexandre de Limas Santana; Adrià Armejach; Marc Casas (PPoPP, 2023)

Characterization of a Coherent Hardware Accelerator Framework for SoCs. - Guillem López-Paradís; Balaji Venu; Adrià Armejach; Miquel Moretó (SAMOS, 2023)

Porting and Optimizing BWA-MEM2 Using the Fujitsu A64FX Processor. - Rubén Langarita; Adrià Armejach; Pablo Ibáñez 001; Jesús Alastruey-Benedé; Miquel Moretó (IEEE ACM Trans. Comput. Biol. Bioinform., 2023)

Exploiting Vector Code Semantics for Efficient Data Cache Prefetching. - Francesc Martínez Palau; Martí Torrents; Adrià Armejach; Marc Casas (ICS, 2024)

A Mess of Memory System Benchmarking, Simulation and Application Profiling. - Pouya Esmaili-Dokht; Francesco Sgherzi; Valéria Soldera Girelli; Isaac Boixaderas; Mariana Carmin; Alireza Monemi; Adrià Armejach; Estanislao Mercadal; Germán Llort; Petar Radojkovic; Miquel Moretó; Judit Giménez; et al. (MICRO, 2024)

A Mess of Memory System Benchmarking, Simulation and Application Profiling. - Pouya Esmaili-Dokht; Francesco Sgherzi; Valéria Soldera Girelli; Isaac Boixaderas; Mariana Carmin; Alireza Momeni; Adrià Armejach; Estanislao Mercadal; Germán Llort; Petar Radojkovic; Miquel Moretó; Judit Giménez; et al. (CoRR, 2024)

GenArchBench: A genomics benchmark suite for arm HPC processors. - Lorién López-Villellas; Rubén Langarita-Benítez; Asaf Badouh; Víctor Soria Pardos; Quim Aguado-Puig; Guillem López-Paradís; Max Doblas; Javier Setoain; Chulho Kim; Makoto Ono; Adrià Armejach; Santiago Marco-Sola; et al. (Future Gener. Comput. Syst., 2024)

SpChar: Characterizing the sparse puzzle via decision trees. - Francesco Sgherzi; Marco Siracusa; Ivan Fernandez; Adrià Armejach; Miquel Moretó (J. Parallel Distributed Comput., 2024)

On Usage of Non-Volatile Memory as Primary Storage for Database Management Systems. - Naveed Ul Mustafa; Adrià Armejach; Ozcan Ozturk 001; Adrián Cristal; Osman S. Unsal (CoRR, 2025)

Ember: A Compiler for Efficient Embedding Operations on Decoupled Access-Execute Architectures. - Marco Siracusa; Olivia Hsu; Víctor Soria Pardos; Joshua Randall 001; Arnaud Grasset; Eric Biscondi; Douglas J. Joseph; Randy Allen; Fredrik Kjolstad; Miquel Moretó Planas; Adrià Armejach (CoRR, 2025)

A Flexible Instruction Set Architecture for Efficient GEMMs. - Alexandre de Limas Santana; Adrià Armejach; Francesc Martínez; Erich Focht; Marc Casas (CoRR, 2025)