POSTER: SPiDRE: Accelerating Sparse Memory Access Patterns. - Adrián Barredo; Jonathan C. Beard; Miquel Moretó (PACT, 2019)

POSTER: An Optimized Predication Execution for SIMD Extensions. - Adrián Barredo; Juan M. Cebrian; Miquel Moretó; Marc Casas; Mateo Valero (PACT, 2019)

Improving Predication Efficiency through Compaction/Restoration of SIMD Instructions. - Adrián Barredo; Juan M. Cebrian; Miquel Moretó; Marc Casas; Mateo Valero (HPCA, 2020)

Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86. - Juan M. Cebrian; Adrián Barredo; Helena Caminal; Miquel Moretó; Marc Casas; Mateo Valero (Future Gener. Comput. Syst., 2020)

Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies. - Adrián Barredo; Juan M. Cebrian; Mateo Valero; Marc Casas; Miquel Moretó (J. Supercomput., 2020)

VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations. - Julian Pavon; Iván Vargas Valdivieso; Adrián Barredo; Joan Marimon; Miquel Moretó; Francesc Moll; Osman S. Unsal; Mateo Valero; Adrián Cristal (HPCA, 2021)

PLANAR: a programmable accelerator for near-memory data rearrangement. - Adrián Barredo; Adrià Armejach; Jonathan C. Beard; Miquel Moretó (ICS, 2021)

Novel techniques to improve the performance and the energy of vector architectures. - Adrián Barredo (2021)

Compiler-Assisted Compaction/Restoration of SIMD Instructions. - Juan M. Cebrian; Thibaud Balem; Adrián Barredo; Marc Casas; Miquel Moretó; Alberto Ros 001; Alexandra Jimborean (IEEE Trans. Parallel Distributed Syst., 2022)

ParaVerser: Harnessing Heterogeneous Parallelism for Affordable Fault Detection in Data Centers. - Minli Julie Liao; Sam Ainsworth; Lev Mukhanov; Adrián Barredo; Markos Kynigos; Timothy M. Jones 001 (DSN, 2025)