SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management. - Rémi Dekimpe; Maxime Schramme; Martin Lefebvre 002; Adrian Kneip; Roghayeh Saeidi; Mathieu Xhonneux; Ludovic Moreau; Marco Gonzalez; Thibault Pirson; David Bol (VLSI Circuits, 2021)

Impact of Analog Non-Idealities on the Design Space of 6T-SRAM Current-Domain Dot-Product Operators for In-Memory Computing. - Adrian Kneip; David Bol (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-Normalization. - Adrian Kneip; Martin Lefebvre 002; Julien Verecken; David Bol (ESSCIRC, 2022)

IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm2 CIM-SRAM With Multi-Bit Analog Batch-Normalization. - Adrian Kneip; Martin Lefebvre 002; Julien Verecken; David Bol (IEEE J. Solid State Circuits, 2023)

A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias. - Adrian Kneip; David Bol (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

EvGNN: An Event-driven Graph Neural Network Accelerator for Edge Vision. - Yufeng Yang; Adrian Kneip; Charlotte Frenkel (CoRR, 2024)

IMAGINE: An 8-to-1b 22nm FD-SOI Compute-In-Memory CNN Accelerator With an End-to-End Analog Charge-Based 0.15-8POPS/W Macro Featuring Distribution-Aware Data Reshaping. - Adrian Kneip; Martin Lefebvre 002; Pol Maistriaux; David Bol (CoRR, 2024)

Bridging the hardware-software co-design gap in analog compute-in-memory accelerators towards edge CNN classification. - Adrian Kneip (2024)

An Event-Based Digital Compute-In-Memory Accelerator with Flexible Operand Resolution and Layer-Wise Weight/Output Stationarity. - Nicolas Chauvaux; Adrian Kneip; Christoph Posch; Kofi Makinwa; Charlotte Frenkel (ISCAS, 2025)