Retargeting the MIPS-II CPU Core to the RISC-V Architecture. - Sebastian Cieslak; Adrian Oleksiak; Krzysztof Marcinek; Witold A. Pleskacz (MIXDES, 2019)

Design and Verification Environment for RISC-V Processor Cores. - Adrian Oleksiak; Sebastian Cieslak; Krzysztof Marcinek; Witold A. Pleskacz (MIXDES, 2019)