A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler. - Francesco Buccoleri; Simone Mattia Dartizio; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Andrea Bevilacqua; Luca Bertulessi; Dmytro Cherniak; Carlo Samori; Andrea L. Lacaita; et al. (CICC, 2022)

A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS. - Agata Iesurum; Davide Manente; Fabio Padovan; Matteo Bassi; Andrea Bevilacqua (ESSCIRC, 2022)

A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching. - Simone Mattia Dartizio; Francesco Buccoleri; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Dmytro Cherniak; Luca Bertulessi; Andrea Bevilacqua; Carlo Samori; Andrea Leonardo Lacaita; et al. (ISSCC, 2022)

A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time. - Simone Mattia Dartizio; Francesco Buccoleri; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Dmytro Cherniak; Luca Bertulessi; Andrea Bevilacqua; Carlo Samori; Andrea L. Lacaita; et al. (IEEE J. Solid State Circuits, 2022)

A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner. - Francesco Buccoleri; Simone Mattia Dartizio; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Dmytro Cherniak; Luca Bertulessi; Andrea Bevilacqua; Carlo Samori; Andrea L. Lacaita; et al. (IEEE J. Solid State Circuits, 2023)

Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs. - Agata Iesurum; Davide Manente; Fabio Padovan; Matteo Bassi; Andrea Bevilacqua (IEEE J. Solid State Circuits, 2024)

A Stacking Technique for High-Swing Low-Phase Noise Class-C Oscillators Using Core Devices in Ultrascaled CMOS Technologies. - Lorenzo Tomasin; Agata Iesurum; Andrea Gobbo; Andrea Neviani; Andrea Bevilacqua (IEEE Trans. Circuits Syst. II Express Briefs, 2024)