An 8-bit 3.2GS/S CMOS time-interleaved SAR ADC with non-buffered input demultiplexing. - Benjamín T. Reyes; Laura Biolato; Agustin C. Galetto; Leandro Passetti; Fredy Solis; Mario R. Hueda (LASCAS, 2018)

An Energy-Efficient Hierarchical Architecture for Time-Interleaved SAR ADC. - Benjamín T. Reyes; Laura Biolato; Agustin C. Galetto; Leandro Passetti; Fredy Solis; Mario R. Hueda (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Backpropagation-Based Background Compensation of Frequency Interleaved ADC for Coherent Optical Receivers. - Leandro Passetti; Agustin C. Galetto; Diego J. Hernando; Damián A. Morero; Benjamín T. Reyes; Mario R. Hueda (ISCAS, 2020)

Background Compensation of Frequency Interleaved DAC for Optical Transceivers. - Agustin C. Galetto; Benjamín T. Reyes; Damián A. Morero; Mario R. Hueda (LASCAS, 2021)

Adaptive Background Compensation of Frequency Interleaved DACs With Application to Coherent Optical Transceivers. - Agustin C. Galetto; Benjamín T. Reyes; Damián A. Morero; Mario R. Hueda (IEEE Access, 2021)

A 4GS/s 8-bit time-interleaved SAR ADC with an energy-efficient architecture in 130 nm CMOS. - Fredy Solis; Álvaro Fernandez Bocco; Agustin C. Galetto; Leandro Passetti; Mario R. Hueda; Benjamín T. Reyes (Int. J. Circuit Theory Appl., 2021)

Backpropagation Based Background Compensation of TI-DAC Errors in High-Speed Transmitters. - Agustin C. Galetto; Benjamín T. Reyes; Damián A. Morero; Mario R. Hueda (MWSCAS, 2022)

Digital Background Compensation of Analog Impairments in Jointly Frequency-Time Interleaved DACs. - Agustin C. Galetto; Juan I. Bonetti; Benjamín T. Reyes; Damián A. Morero; Mario R. Hueda (IEEE Access, 2023)