A parallel tabu search algorithm for VLSI standard-cell placement. - Sadiq M. Sait; Habib Youssef; Hassan R. Barada; Ahmad A. Al-Yamani (ISCAS, 2000)

Performance Evaluation of Checksum-Based ABFT. - Ahmad A. Al-Yamani; Nahmsuk Oh; Edward J. McCluskey (DFT, 2001)

HPTS: heterogeneous parallel tabu search for VLSI placement. - Ahmad A. Al-Yamani; Sadiq M. Sait; Hassan R. Barada (IEEE Congress on Evolutionary Computation, 2002)

Testing Digital Circuits with Constraints. - Ahmad A. Al-Yamani; Subhasish Mitra; Edward J. McCluskey (DFT, 2002)

Parallelizing Tabu Search on a Cluster of Heterogeneous Workstations. - Ahmad A. Al-Yamani; Sadiq M. Sait; Habib Youssef; Hassan R. Barada (J. Heuristics, 2002)

Seed encoding with LFSRs and cellular automata. - Ahmad A. Al-Yamani; Edward J. McCluskey (DAC, 2003)

Parallel Tabu Search in a Heterogeneous Environment. - Ahmad A. Al-Yamani; Sadiq M. Sait; Hassan R. Barada; Habib Youssef (IPDPS, 2003)

Built-In Reseeding for Serial Bist. - Ahmad A. Al-Yamani; Edward J. McCluskey (VTS, 2003)

Bist Reseeding with very few Seeds. - Ahmad A. Al-Yamani; Subhasish Mitra; Edward J. McCluskey (VTS, 2003)

Test quality for high level structural test. - Ahmad A. Al-Yamani; Edward J. McCluskey (HLDVT, 2004)

ELF-Murphy Data on Defects and Test Sets. - Edward J. McCluskey; Ahmad A. Al-Yamani; Chien-Mo James Li; Chao-Wen Tseng; Erik H. Volkerink; François-Fabien Ferhani; Edward Li; Subhasish Mitra (VTS, 2004)

Should Illinois-Scan Based Architectures be Centralized or Distributed? - Ahmad A. Al-Yamani; Narendra Devta-Prasanna; Arun Gunda (DFT, 2005)

BIST-Guided ATPG. - Ahmad A. Al-Yamani; Edward J. McCluskey (ISQED, 2005)

Segmented Addressable Scan Architecture. - Ahmad A. Al-Yamani; Erik Chmelar; Mikhail Grinchuck (VTS, 2005)

Effective TARO Pattern Generation. - Intaik Park; Ahmad A. Al-Yamani; Edward J. McCluskey (VTS, 2005)

Optimized reseeding by seed ordering and encoding. - Ahmad A. Al-Yamani; Subhasish Mitra; Edward J. McCluskey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Test chip experimental results on high-level structural test. - Ahmad A. Al-Yamani; Edward J. McCluskey (ACM Trans. Design Autom. Electr. Syst., 2005)

DFT for controlled-impedance I/O buffers. - Ahmad A. Al-Yamani (DAC, 2006)

Systematic Scan Reconfiguration. - Ahmad A. Al-Yamani; Narendra Devta-Prasanna; Arun Gunda (ASP-DAC, 2007)

A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decompos. - Aiman H. El-Maleh; Mustafa Imran Ali; Ahmad A. Al-Yamani (ATS, 2007)

Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm. - S. Ramsundar; Ahmad A. Al-Yamani; Dhiraj K. Pradhan (ISQED, 2007)

High defect tolerant low cost memory chips. - Costas Argyrides; Ahmad A. Al-Yamani; Dhiraj K. Pradhan (SoCC, 2007)

Energy-delay efficient test. - Ahmad A. Al-Yamani (IET Comput. Digit. Tech., 2007)

Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration. - Ahmad A. Al-Yamani; Narendra Devta-Prasanna; Erik Chmelar; M. Grinchuk; Arun Gunda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

A Defect Tolerance Scheme for Nanotechnology Circuits. - Ahmad A. Al-Yamani; S. Ramsundar; Dhiraj K. Pradhan (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Comparative study of centralised and distributed compatibility-based test data compression. - Ahmad A. Al-Yamani; Narendra Devta-Prasanna; Arun Gunda (IET Comput. Digit. Tech., 2008)

Increasing memory yield in future technologies through innovative design. - Costas Argyrides; Ahmad A. Al-Yamani; Carlos Arthur Lang Lisbôa; Luigi Carro; Dhiraj K. Pradhan (ISQED, 2009)

Reconfigurable broadcast scan compression using relaxation-based test vector decomposition. - Aiman H. El-Maleh; Mustafa Imran Ali; Ahmad A. Al-Yamani (IET Comput. Digit. Tech., 2009)

Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns. - Ahmad A. Al-Yamani; Edward J. McCluskey (J. Electron. Test., 2010)