High-Speed Division Algorithm for Residue Number System. - Ahmad A. Hiasat; Hoda S. Abdel-Aty-Zohdy (ISCAS, 1995)

Semi-custom VLSI design for RNS multipliers using combinational logic approach. - Ahmad A. Hiasat (ICECS, 1996)

Design and Implementation of An RNS Division Algorithmm. - Ahmad A. Hiasat; Hoda S. Abdel-Aty-Zohdy (IEEE Symposium on Computer Arithmetic, 1997)

Full-custom VLSI design of a new high-speed modular adder structures. - Ahmad A. Hiasat (ICECS, 1999)

Semi-Custom VLSI Design and Implementation of a New Efficient RNS Division Algorithm. - Ahmad A. Hiasat; Hoda S. Abdel-Aty-Zohdy (Comput. J., 1999)

New Efficient Structure for a Modular Multiplier for RNS. - Ahmad A. Hiasat (IEEE Trans. Computers, 2000)

Semi-custom VLSI chip implementation of a new two-dimensional separable median filtering algorithm. - Ahmad A. Hiasat (ICECS, 2001)

On the Theory of Error Control Based on Moduli with Common Factors. - Andraos Sweidan; Ahmad A. Hiasat (Reliab. Comput., 2001)

High-Speed and Reduced-Area Modular Adder Structures for RNS. - Ahmad A. Hiasat (IEEE Trans. Computers, 2002)

An arithmetic residue to binary conversion technique. - Ahmad A. Hiasat (Integr., 2003)

Bit-serial architecture for rank order and stack filters. - Ahmad A. Hiasat; Omar Hasan (Integr., 2003)

Residue number system to binary converter for the moduli set (2n-1, 2n-1, 2n+1). - Ahmad A. Hiasat; Andraos Sweidan (J. Syst. Archit., 2003)

A Suggestion for a Fast Residue Multiplier for a Family of Moduli of the Form (2n - (2p [plusmn] 1)). - Ahmad A. Hiasat (Comput. J., 2004)

Limiter discriminator detection of narrow-band duobinary FSK in a land mobile channel. - Omar Hasan; Ahmad A. Hiasat (Int. J. Commun. Syst., 2004)

A Suggestion for a New RNS-Based Multiplier for a Family of Moduli. - Ahmad A. Hiasat (Int. J. Comput. Their Appl., 2004)

VLSI implementation of new arithmetic residue to binary decoders. - Ahmad A. Hiasat (IEEE Trans. Very Large Scale Integr. Syst., 2005)

A Sign Detector for a Group of Three-Moduli Sets. - Ahmad A. Hiasat (IEEE Trans. Computers, 2016)

Efficient RNS Scalers for the Extended Three-Moduli Set (2n-1, 2n+p, 2n+1). - Ahmad A. Hiasat (IEEE Trans. Computers, 2017)

A Reverse Converter and Sign Detectors for an Extended RNS Five-Moduli Set. - Ahmad A. Hiasat (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

An Efficient Reverse Converter for the Three-Moduli Set ( $ 2^{n+1}-1, 2^{n}, 2^{n}-1$ ). - Ahmad A. Hiasat (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A Residue-to-Binary Converter for the Extended Four-Moduli Set {2n-1, 2n+1, 22n+1, 22n+p}. - Ahmad A. Hiasat (IEEE Trans. Very Large Scale Integr. Syst., 2017)

New Residue Number System Scaler for the Three-Moduli Set {2n+1 - 1, 2n, 2n - 1}. - Ahmad A. Hiasat (Comput., 2018)

General modular adder designs for residue number system applications. - Ahmad A. Hiasat (IET Circuits Devices Syst., 2018)

Sign detector for the extended four-moduli set { 2n - 1 , 2n + 1 , 22n + 1 , 2n + k }. - Ahmad A. Hiasat (IET Comput. Digit. Tech., 2018)

On the Design of RNS Inter-Modulo Processing Units for the Arithmetic-Friendly Moduli Sets {2n+k, 2n - 1, 2n+1 - 1}. - Ahmad A. Hiasat; Leonel Sousa (Comput. J., 2019)

A Residue-to-Binary Converter with an Adjustable Structure for an Extended RNS Three-Moduli Set. - Ahmad A. Hiasat (J. Circuits Syst. Comput., 2019)

Sign Identifier for the Enhanced Three Moduli Set {2 n + k , 2 n - 1, 2 n+ 1 - 1}. - Ahmad A. Hiasat; Leonel Sousa (J. Signal Process. Syst., 2019)

A Scaler Design for the RNS Three-Moduli Set {2n+1-1, 2n, 2n-1} Based on Mixed-Radix Conversion. - Ahmad A. Hiasat (J. Circuits Syst. Comput., 2020)

An arithmetic scaler circuit design for the expanded four-moduli set {2k-1, 2k+1, 22k+1, 22k}. - Ahmad A. Hiasat (Comput. Electr. Eng., 2022)