Video-Rate Stereo Depth Measurement on Programmable Hardware. - Ahmad Darabiha; Jonathan Rose; W. James MacLean (CVPR (1), 2003)

Reconfigurable Molecular Dynamics Simulator. - Navid Azizi; Ian Kuon; Aaron Egier; Ahmad Darabiha; Paul Chow (FCCM, 2004)

FPGA-based supercomputing: an implementation for molecular dynamics. - Ian Kuon; Navid Azizi; Ahmad Darabiha; Aaron Egier; Paul Chow (FPGA, 2004)

Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity. - Ahmad Darabiha; Anthony Chan Carusone; Frank R. Kschischang (ISCAS (5), 2005)

A bit-serial approximate min-sum LDPC decoder and FPGA implementation. - Ahmad Darabiha; Anthony Chan Carusone; Frank R. Kschischang (ISCAS, 2006)

Reconfigurable hardware implementation of a phase-correlation stereoalgorithm. - Ahmad Darabiha; W. James MacLean; Jonathan Rose (Mach. Vis. Appl., 2006)

A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS. - Ahmad Darabiha; Anthony Chan Carusone; Frank R. Kschischang (CICC, 2007)

Power Reduction Techniques for LDPC Decoders. - Ahmad Darabiha; Anthony Chan Carusone; Frank R. Kschischang (IEEE J. Solid State Circuits, 2008)

Block-Interlaced LDPC Decoders With Reduced Interconnect Complexity. - Ahmad Darabiha; Anthony Chan Carusone; Frank R. Kschischang (IEEE Trans. Circuits Syst. II Express Briefs, 2008)