15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS. - Ahmed Elkholy; Amr Elshazly; Saurabh Saxena; Guanghua Shu; Pavan Kumar Hanumolu (ISSCC, 2014)

A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC. - Ahmed Elkholy; Tejasvi Anand; Woo-Seok Choi; Amr Elshazly; Pavan Kumar Hanumolu (VLSIC, 2014)

A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. - Romesh Kumar Nandwana; Tejasvi Anand; Saurabh Saxena; Seong Joong Kim; Mrunmay Talegaonkar; Ahmed Elkholy; Woo-Seok Choi; Amr Elshazly; Pavan Kumar Hanumolu (VLSIC, 2014)

A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. - Mrunmay Talegaonkar; Tejasvi Anand; Ahmed Elkholy; Amr Elshazly; Romesh Kumar Nandwana; Saurabh Saxena; Brian Young; Woo-Seok Choi; Pavan Kumar Hanumolu (VLSIC, 2014)

A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter. - Ahmed Elkholy; Saurabh Saxena; Romesh Kumar Nandwana; Amr Elshazly; Pavan Kumar Hanumolu (CICC, 2015)

3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS. - Tejasvi Anand; Mrunmay Talegaonkar; Ahmed Elkholy; Saurabh Saxena; Amr Elshazly; Pavan Kumar Hanumolu (ISSCC, 2015)

10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS. - Ahmed Elkholy; Mrunmay Talegaonkar; Tejasvi Anand; Pavan Kumar Hanumolu (ISSCC, 2015)

A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS. - Saurabh Saxena; Guanghua Shu; Romesh Kumar Nandwana; Mrunmay Talegaonkar; Ahmed Elkholy; Tejasvi Anand; Seong Joong Kim; Woo-Seok Choi; Pavan Kumar Hanumolu (VLSIC, 2015)

A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links. - Tejasvi Anand; Mrunmay Talegaonkar; Ahmed Elkholy; Saurabh Saxena; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2015)

A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC. - Ahmed Elkholy; Tejasvi Anand; Woo-Seok Choi; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2015)

Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers. - Ahmed Elkholy; Mrunmay Talegaonkar; Tejasvi Anand; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2015)

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. - Romesh Kumar Nandwana; Tejasvi Anand; Saurabh Saxena; Seong Joong Kim; Mrunmay Talegaonkar; Ahmed Elkholy; Woo-Seok Choi; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2015)

10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS. - Ahmed Elkholy; Ahmed Elmallah; Mohamed Elzeftawi; Ken Chang; Pavan Kumar Hanumolu (ISSCC, 2016)

23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS. - Guanghua Shu; Woo-Seok Choi; Saurabh Saxena; Seong Joong Kim; Mrunmay Talegaonkar; Romesh Kumar Nandwana; Ahmed Elkholy; Da Wei; Timir Nandi; Pavan Kumar Hanumolu (ISSCC, 2016)

19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS. - Junheng Zhu; Romesh Kumar Nandwana; Guanghua Shu; Ahmed Elkholy; Seong Joong Kim; Pavan Kumar Hanumolu (ISSCC, 2016)

A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider. - Ahmed Elkholy; Saurabh Saxena; Romesh Kumar Nandwana; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2016)

A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition. - Guanghua Shu; Woo-Seok Choi; Saurabh Saxena; Mrunmay Talegaonkar; Tejasvi Anand; Ahmed Elkholy; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2016)

Digital enhancement techniques for fractional-N frequency synthesizers - Ahmed Elkholy (2016)

A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS. - Junheng Zhu; Makrand Mahalley; Guanghua Shu; Woo-Seok Choi; Romesh Kumar Nandwana; Ahmed Elkholy; Bibhudatta Sahoo 002; Pavan Kumar Hanumolu (CICC, 2017)

8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS. - Daniel Coombs; Ahmed Elkholy; Romesh Kumar Nandwana; Ahmed Elmallah; Pavan Kumar Hanumolu (ISSCC, 2017)

29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS. - Romesh Kumar Nandwana; Saurabh Saxena; Ahmed Elkholy; Mrunmay Talegaonkar; Junheng Zhu; Woo-Seok Choi; Ahmed Elmallah; Pavan Kumar Hanumolu (ISSCC, 2017)

A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver. - Saurabh Saxena; Guanghua Shu; Romesh Kumar Nandwana; Mrunmay Talegaonkar; Ahmed Elkholy; Tejasvi Anand; Woo-Seok Choi; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2017)

A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. - Mrunmay Talegaonkar; Tejasvi Anand; Ahmed Elkholy; Amr Elshazly; Romesh Kumar Nandwana; Saurabh Saxena; Brian Young; Woo-Seok Choi; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2017)

A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS. - Junheng Zhu; Romesh Kumar Nandwana; Guanghua Shu; Ahmed Elkholy; Seong Joong Kim; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2017)

A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS. - Ahmed Elmallah; Mostafa Gamal Ahmed; Ahmed Elkholy; Woo-Seok Choi; Pavan Kumar Hanumolu (CICC, 2018)

A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR. - Dongwook Kim; Woo-Seok Choi; Ahmed Elkholy; Jack Kenney; Pavan Kumar Hanumolu (CICC, 2018)

A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS. - Karim M. Megawer; Ahmed Elkholy; Daniel Coombs; Mostafa Gamal Ahmed; Ahmed Elmallah; Pavan Kumar Hanumolu (ISSCC, 2018)

A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS. - Mostafa Gamal Ahmed; Mrunmay Talegaonkar; Ahmed Elkholy; Guanghua Shu; Ahmed Elmallah; Alexander V. Rylyakov; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2018)

A 6.75-8.25-GHz -250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier. - Ahmed Elkholy; Ahmed Elmallah; Mostafa Gamal Ahmed; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2018)

Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers. - Ahmed Elkholy; Saurabh Saxena; Guanghua Shu; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2018)

A 5GHz 245fsrms 8mW Ring Oscillator-based Digital Frequency Synthesizer. - Amr Khashaba; Ahmed Elkholy; Karim M. Megawer; Mostafa Gamal Ahmed; Pavan Kumar Hanumolu (CICC, 2019)

A 54MHz Crystal Oscillator With 30× 18.5 Start-Up Time Reduction Using 2-Step Injection in 65nm CMOS. - Karim M. Megawer; Nilanjan Pal; Ahmed Elkholy; Mostafa Gamal Ahmed; Amr Khashaba; Danielle Griffith; Pavan Kumar Hanumolu (ISSCC, 2019)

A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler. - Ahmed Elkholy; Daniel Coombs; Romesh Kumar Nandwana; Ahmed Elmallah; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2019)

A 15-Gb/s Sub-Baud-Rate Digital CDR. - Dongwook Kim; Woo-Seok Choi; Ahmed Elkholy; Jack Kenney; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2019)

Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers. - Karim M. Megawer; Ahmed Elkholy; Mostafa Gamal Ahmed; Ahmed Elmallah; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2019)

A Fast Startup CMOS Crystal Oscillator Using Two-Step Injection. - Karim M. Megawer; Nilanjan Pal; Ahmed Elkholy; Mostafa Gamal Ahmed; Amr Khashaba; Danielle Griffith; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2019)

A 6 $ mu$ W ±50 ppm/°C ±1500 ppm/V 1.5 MHz $RC$ Oscillator Using Self-Regulation. - Tianyu Wang 006; Danielle Griffith; Mostafa Gamal Ahmed; Junheng Zhu; Da Wei; Ahmed Elkholy; Ahmed Elmallah; Pavan Kumar Hanumolu (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Arabian horse identification based on whale optimised multi-class support vector machine. - Ayat Taha; Ashraf Darwish; Aboul Ella Hassanien; Ahmed Elkholy (Int. J. Comput. Appl. Technol., 2020)

A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques. - Amr Khashaba; Ahmed Elkholy; Karim M. Megawer; Mostafa Gamal Ahmed; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2020)

A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS. - Dongwook Kim; Mostafa Gamal Ahmed; Woo-Seok Choi; Ahmed Elkholy; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2020)

A 3.2GHz 405fsrms jitter -237.2dB-FoMJIT ring-based fractional-N synthesizer using two-step quantization noise cancellation and piecewise-linear nonlinearity correction. - Ahmed Elmallah; Junheng Zhu; Amr Khashaba; Karim M. Megawer; Ahmed Elkholy; Pavan Kumar Hanumolu (CICC, 2021)

A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling. - Mostafa Gamal Ahmed; Dongwook Kim; Romesh Kumar Nandwana; Ahmed Elkholy; Kadaba R. Lakshmikumar; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2021)

A 3.2-GHz 405 fsrms Jitter -237.2 dB FoMJIT Ring-Based Fractional-N Synthesizer. - Ahmed Elmallah; Junheng Zhu; Amr Khashaba; Karim M. Megawer; Ahmed Elkholy; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2022)