A neural net based self organising scheduling algorithm. - Ahmed Hemani; Adam Postula (EURO-DAC, 1990)

Cell placement by self-organisation. - Ahmed Hemani; Adam Postula (Neural Networks, 1990)

Self-Organization and its Application to Binding. - Ahmed Hemani (VLSI Design, 1993)

Hardware/software partitioning and minimizing memory interface traffic. - Axel Jantsch; Peeter Ellervee; Ahmed Hemani; Johnny Öberg; Hannu Tenhunen (EURO-DAC, 1994)

Application of High-Level Synthesis in an Industrial Project. - Ahmed Hemani; Börje Karlsson 002; Mats Fredriksson; Kurt Nordqvist; Björn Fjellborg (VLSI Design, 1994)

Flexible Codesign Target Architecture for Early Prototyping of CMIST Systems. - Kalle Tammemäe; Mattias O'Nils; Ahmed Hemani (FPL, 1996)

Grammar-Based Hardware Synthesis of Data Communication Protocols. - Johnny Öberg; Anshul Kumar; Ahmed Hemani (ISSS, 1996)

A Rule-Based Approach for Improving Allocation of Filter Structures in HLS. - Johnny Öberg; Jouni Isoaho; Peeter Ellervee; Axel Jantsch; Ahmed Hemani (VLSI Design, 1996)

A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts. - Bengt Svantesson; Ahmed Hemani; Peeter Ellervee; Adam Postula; Johnny Öberg; Axel Jantsch; Hannu Tenhunen (VLSI Design, 1996)

System oriented VLSI curriculum at KTH. - Lars Hellberg; Ahmed Hemani; Jouni Isoaho; Axel Jantsch; Mehran Mokhtari; Hannu Tenhunen (MSE, 1997)

Scheduling of Outputs in Grammar-based Hardware Synthesis of Data Communication Protocols. - Johnny Öberg; Ahmed Hemani; Anshul Kumar (DATE, 1998)

Specification of Exception Handling in Grammar-Based Hardware Synthesis. - Johnny Öberg; Anshul Kumar; Ahmed Hemani (EUROMICRO, 1998)

A Methodology and Algorithms for Efficient Interprocess Communication Synthesis from System Description in SDL. - Bengt Svantesson; Shashi Kumar; Ahmed Hemani (VLSI Design, 1998)

Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style. - Ahmed Hemani; Thomas Meincke; Shashi Kumar; Adam Postula; Thomas Olsson 001; Peter Nilsson 001; Johnny Öberg; Peeter Ellervee; Dan Lundqvist (DAC, 1999)

The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems. - Axel Jantsch; Shashi Kumar; Ahmed Hemani (DATE, 1999)

Exploiting Data Transfer Locality in Memory Mapping. - Peeter Ellervee; Ahmed Hemani; Miguel Miranda; Francky Catthoor (EUROMICRO, 1999)

Globally asynchronous locally synchronous architecture for large high-performance ASICs. - Thomas Meincke; Ahmed Hemani; Shashi Kumar; Peeter Ellervee; Johnny Öberg; Thomas Olsson 001; Peter Nilsson 001; Dan Lindqvist; Hannu Tenhunen (ISCAS (2), 1999)

System Level Virtual Prototyping of DSP ASICs Using Grammar Based Approach. - Ahmed Hemani; Johnny Öberg; Abhijit K. Deb; Dan Lindqvist; Björn Fjellborg (IEEE International Workshop on Rapid System Prototyping, 1999)

System-level data format exploration for dynamically allocated data structures. - Peeter Ellervee; Miguel Miranda; Francky Catthoor; Ahmed Hemani (DAC, 2000)

Development of Programmable Architecture for Base-Band Processing. - Simon Leung; Adam Postula; Ahmed Hemani (EUROMICRO, 2000)

Reconfigurable Architecture for Base-band Data Processing. - Simon Leung; Adam Postula; Ahmed Hemani (PDPTA, 2000)

System Level Virtual Prototyping of DSP SOCs Using Grammar Based Approach. - Ahmed Hemani; Abhijit K. Deb; Johnny Öberg; Adam Postula; Dan Lindqvist; Björn Fjellborg (Des. Autom. Embed. Syst., 2000)

A Metamodel for Studying Concepts in Electronic System Design. - Axel Jantsch; Shashi Kumar; Ahmed Hemani (IEEE Des. Test Comput., 2000)

Grammar-based hardware synthesis from port-size independent specifications. - Johnny Öberg; Anshul Kumar; Ahmed Hemani (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Test Strategies on Functionally Partitioned Module-Based Programmable Architecture for Base-Band Processing. - Simon Leung; Adam Postula; Ahmed Hemani (DSD, 2001)

Hardware Software Codesign of DSP System Using Grammar Based Approach. - Abhijit K. Deb; Ahmed Hemani; Johnny Öberg; Adam Postula; Dan Lindqvist (VLSI Design, 2001)

Grammar-based design of embedded systems. - Johnny Öberg; Mattias O'Nils; Axel Jantsch; Adam Postula; Ahmed Hemani (J. Syst. Archit., 2001)

System-level data-format exploration for dynamically allocated datastructures. - Peeter Ellervee; Miguel Miranda; Francky Catthoor; Ahmed Hemani (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

A Network on Chip Architecture and Design Methodology. - Shashi Kumar; Axel Jantsch; Mikael Millberg; Johnny Öberg; Juha-Pekka Soininen; Martti Forsell; Kari Tiensyrjä; Ahmed Hemani (ISVLSI, 2002)

Dynamic memory management methodology applied to embedded telecom network systems. - Chantal Ykman-Couvreur; Jurgen Lambrecht; Diederik Verkest; Francky Catthoor; Bengt Svantesson; Ahmed Hemani; F. Wolf (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Energy and Performance Model of a SPARC Leon3 Processor. - Sandro Penolazzi; Luca Bolognino; Ahmed Hemani (DSD, 2009)

Option Based Evaluation: Security Evaluation of IT Products Based on Options Theory. - Haider Abbas; Louise Yngström; Ahmed Hemani (ECBS-EERC, 2009)

A flexible communication scheme for rationally-related clock frequencies. - Jean-Michel Chabloz; Ahmed Hemani (ICCD, 2009)

Adaptability infrastructure for bridging IT security evaluation and options theory. - Haider Abbas; Louise Yngström; Ahmed Hemani (SIN, 2009)

Morphable DPU: Smart and efficient data path for signal processing applications. - Muhammad Ali Shami; Ahmed Hemani (SiPS, 2009)

A General Approach to High-Level Energy and Performance Estimation in SoCs. - Sandro Penolazzi; Ahmed Hemani; Luca Bolognino (VLSI Design, 2009)

A General Approach to High-Level Energy and Performance Estimation in System-on-Chip Architectures. - Sandro Penolazzi; Ahmed Hemani; Luca Bolognino (J. Low Power Electron., 2009)

Predicting energy and performance overhead of Real-Time Operating Systems. - Sandro Penolazzi; Ingo Sander; Ahmed Hemani (DATE, 2010)

Lowering the latency of interfaces for rationally-related frequencies. - Jean-Michel Chabloz; Ahmed Hemani (ICCD, 2010)

Distributed DVFS using rationally-related frequencies and discrete voltage levels. - Jean-Michel Chabloz; Ahmed Hemani (ISLPED, 2010)

Improving performance of fading channel simulators by use of uniformly distributed random numbers. - Jamshaid Sarwar Malik; Ben Slimane; Ahmed Hemani; Nasirud Din Gohar (ISSPIT, 2010)

The MOSART Mapping Optimization for Multi-Core ARchiTectures. - Bernard Candaele; Sylvain Aguirre; Michel Sarlotte; Iraklis Anagnostopoulos; Sotirios Xydis; Alexandros Bartzas; Dimitris Bekiaris; Dimitrios Soudris; Zhonghai Lu; Xiaowen Chen; Jean-Michel Chabloz; Ahmed Hemani; et al. (ISVLSI (Selected papers), 2010)

Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach. - Bernard Candaele; Sylvain Aguirre; Michel Sarlotte; Iraklis Anagnostopoulos; Sotirios Xydis; Alexandros Bartzas; Dimitris Bekiaris; Dimitrios Soudris; Zhonghai Lu; Xiaowen Chen; Jean-Michel Chabloz; Ahmed Hemani; et al. (ISVLSI, 2010)

A Coarse Grain Reconfigurable Architecture for sequence alignment problems in bio-informatics. - Pei Liu 003; Ahmed Hemani (SASP, 2010)

Control Scheme for a CGRA. - Muhammad Ali Shami; Ahmed Hemani (SBAC-PAD, 2010)

Inferring Energy and Performance Cost of RTOS in Priority-Driven Scheduling. - Sandro Penolazzi; Ingo Sander; Ahmed Hemani (SIES, 2010)

Address generation scheme for a coarse grain reconfigurable architecture. - Muhammad Ali Shami; Ahmed Hemani (ASAP, 2011)

Predicting bus contention effects on energy and performance in multi-processor SoCs. - Sandro Penolazzi; Ingo Sander; Ahmed Hemani (DATE, 2011)

Low-Latency and Low-Overhead Mesochronous and Plesiochronous Synchronizers. - Jean-Michel Chabloz; Ahmed Hemani (DSD, 2011)

Optimal Selection of Function Implementation in a Hierarchical Configware Synthesis Method for a Coarse Grain Reconfigurable Architecture. - Fahimeh Jafari; Shuo Li 002; Ahmed Hemani (DSD, 2011)

Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architectures. - Syed M. A. H. Jafri; Ahmed Hemani; Kolin Paul; Juha Plosila; Hannu Tenhunen (FPT, 2011)

A GALS Network-on-Chip based on rationally-related frequencies. - Jean-Michel Chabloz; Ahmed Hemani (ICCD, 2011)

Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures. - Syed M. A. H. Jafri; Ahmed Hemani; Kolin Paul; Juha Plosila; Hannu Tenhunen (IPDPS Workshops, 2011)

An efficient hardware implementation of high quality AWGN generator using Box-Muller method. - Jamshaid Sarwar Malik; Jameel Nawaz Malik; Ahmed Hemani; Nasirud Din Gohar (ISCIT, 2011)

A coarse-grained reconfigurable protocol processor. - Mohammad Badawi; Ahmed Hemani (SoC, 2011)

Synchronizing distributed state machines in a coarse grain reconfigurable architecture. - Omer Malik; Ahmed Hemani (SoC, 2011)

A Coarse-Grained Reconfigurable Processor for Sequencing and Phylogenetic Algorithms in Bioinformatics. - Pei Liu 003; Fatemeh O. Ebrahim; Ahmed Hemani; Kolin Paul (ReConFig, 2011)

Generating high tail accuracy Gaussian Random Numbers in hardware using central limit theorem. - Jamshaid Sarwar Malik; Jameel Nawaz Malik; Ahmed Hemani; Nasirud Din Gohar (VLSI-SoC, 2011)

A Reconfigurable Processor for Phylogenetic Inference. - Pei Liu 003; Ahmed Hemani; Kolin Paul (VLSI Design, 2011)

A Library Development Framework for a Coarse Grain Reconfigurable Architecture. - Omer Malik; Ahmed Hemani; Muhammad Ali Shami (VLSI Design, 2011)

NoC Based Distributed Partitionable Memory System for a Coarse Grain Reconfigurable Architecture. - Muhammad Adeel Tajammul; Muhammad Ali Shami; Ahmed Hemani; Sridharan Moorthi (VLSI Design, 2011)

Addressing Dynamic Issues in Information Security Management. - Haider Abbas; Christer Magnusson; Louise Yngström; Ahmed Hemani (Inf. Manag. Comput. Secur., 2011)

Improved Bioinformatics Processing Unit for Multiple Applications. - Pei Liu 003; Ahmed Hemani; Kolin Paul (IPDPS Workshops, 2012)

Classification of Massively Parallel Computer Architectures. - Muhammad Ali Shami; Ahmed Hemani (IPDPS Workshops, 2012)

Segmented Bus Based Path Setup Scheme for a Distributed Memory Architecture. - Muhammad Adeel Tajammul; Muhammad Ali Shami; Ahmed Hemani (MCSoC, 2012)

Self-adaptive Noc Power Management with Dual-level Agents - Architecture and Implementation. - Syed M. A. H. Jafri; Liang Guang; Axel Jantsch; Kolin Paul; Ahmed Hemani; Hannu Tenhunen (PECCS, 2012)

A pragma based approach for mapping MATLAB applications on a coarse grained reconfigurable architecture. - Omer Malik; Ahmed Hemani (SBCCI, 2012)

Low-Latency No-Handshake GALS Interfaces for Fast-Receiver Links. - Jean-Michel Chabloz; Ahmed Hemani (VLSI Design, 2012)

Effort, resources, and abstraction vs performance in high-level synthesis: finding new answers to an old question. - Jamshaid Sarwar Malik; Paolo Palazzari; Ahmed Hemani (SIGARCH Comput. Archit. News, 2012)

Unifying CORDIC and Box-Muller algorithms: An accurate and efficient Gaussian Random Number generator. - Jamshaid Sarwar Malik; Ahmed Hemani; Nasirud Din Gohar (ASAP, 2013)

Private configuration environments (PCE) for efficient reconfiguration, in CGRAs. - Muhammad Adeel Tajammul; Syed M. A. H. Jafri; Ahmed Hemani; Juha Plosila; Hannu Tenhunen (ASAP, 2013)

System level synthesis of hardware for DSP applications using pre-characterized function implementations. - Shuo Li 002; Nasim Farahini; Ahmed Hemani; Kathrin Rosvall; Ingo Sander (CODES+ISSS, 2013)

Distributed Runtime Computation of Constraints for Multiple Inner Loops. - Nasim Farahini; Ahmed Hemani; Kolin Paul (DSD, 2013)

Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs. - Syed M. A. H. Jafri; Stanislaw J. Piestrak; Kolin Paul; Ahmed Hemani; Juha Plosila; Hannu Tenhunen (DSD, 2013)

Global Interconnect and Control Synthesis in System Level Architectural Synthesis Framework. - Shuo Li 002; Ahmed Hemani (DSD, 2013)

Global Control and Storage Synthesis for a System Level Synthesis Approach. - Shuo Li 002; Nasim Farahini; Ahmed Hemani (FCCM, 2013)

A code generation method for system-level synthesis on ASIC, FPGA and manycore CGRA. - Shuo Li 002; Jamshaid Sarwar Malik; Shaoteng Liu; Ahmed Hemani (MES, 2013)

39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation. - Nasim Farahini; Shuo Li 002; Muhammad Adeel Tajammul; Muhammad Ali Shami; Guo Chen; Ahmed Hemani; Wei Ye (ISCAS, 2013)

High performance 3D-FFT implementation. - U. Nidhi; Kolin Paul; Ahmed Hemani; Anshul Kumar (ISCAS, 2013)

Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells. - Syed M. A. H. Jafri; Ozan Bag; Ahmed Hemani; Nasim Farahini; Kolin Paul; Juha Plosila; Hannu Tenhunen (ISQED, 2013)

Implementation and evaluation of configuration scrubbing on CGRAs: A case study. - Syed M. A. H. Jafri; Stanislaw J. Piestrak; Ahmed Hemani; Kolin Paul; Juha Plosila; Hannu Tenhunen (ISSoC, 2013)

Memory allocation and optimization in system-level architectural synthesis. - Shuo Li 002; Ahmed Hemani (ReCoSoC, 2013)

Energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAs. - Syed M. A. H. Jafri; Muhammad Adeel Tajammul; Ahmed Hemani; Kolin Paul; Juha Plosila; Hannu Tenhunen (ICSAMOS, 2013)

Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes. - Syed M. A. H. Jafri; Liang Guang; Ahmed Hemani; Kolin Paul; Juha Plosila; Hannu Tenhunen (Microprocess. Microsystems, 2013)

Power-aware dynamic memory management on many-core platforms utilizing DVFS. - Iraklis Anagnostopoulos; Jean-Michel Chabloz; Ioannis Koutras; Alexandros Bartzas; Ahmed Hemani; Dimitrios Soudris (ACM Trans. Embed. Comput. Syst., 2013)

Customizable coarse-grained energy-efficient reconfigurable packet processing architecture. - Mohammad Badawi; Ahmed Hemani; Zhonghai Lu (ASAP, 2014)

A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain. - Nasim Farahini; Ahmed Hemani; Anders Lansner; Fabien Clermidy; Christer Svensson (ASP-DAC, 2014)

Spiking brain models: Computation, memory and communication constraints for custom hardware implementation. - Anders Lansner; Ahmed Hemani; Nasim Farahini (ASP-DAC, 2014)

Case Study: Constraint Programming in a System Level Synthesis Framework. - Shuo Li 002; Ahmed Hemani (CP, 2014)

Morphable Compression Architecture for Efficient Configuration in CGRAs. - Syed Mohammad Asad Hassan Jafri; Muhammad Adeel Tajammul; Masoud Daneshtalab; Ahmed Hemani; Kolin Paul; Peeter Ellervee; Juha Plosila; Hannu Tenhunen (DSD, 2014)

Three-Dimensional Design Space Exploration for System Level Synthesis. - Shuo Li 002; Ahmed Hemani (DSD, 2014)

Customizable Compression Architecture for Efficient Configuration in CGRAs. - Syed M. A. H. Jafri; Muhammad Adeel Tajammul; Masoud Daneshtalab; Ahmed Hemani; Kolin Paul; Peeter Ellervee; Juha Plosila; Hannu Tenhunen (FCCM, 2014)

Accurate and Efficient Three Level Design Space Exploration Based on Constraints Satisfaction Optimization Problem Solver. - Shuo Li 002; Ahmed Hemani (FCCM, 2014)

TransPar: Transformation based dynamic Parallelism for low power CGRAs. - Syed M. A. H. Jafri; Guilermo Serrano; Masoud Daneshtalab; Naeem Abbas; Ahmed Hemani; Kolin Paul; Juha Plosila; Hannu Tenhunen (FPL, 2014)

NeuroCGRA: A CGRA with support for neural networks. - Syed M. A. H. Jafri; Tuan Nguyen Gia; Sergei Dytckov; Masoud Daneshtalab; Ahmed Hemani; Juha Plosila; Hannu Tenhunen (HPCS, 2014)

Exploring Spiking Neural Network on Coarse-Grain Reconfigurable Architectures. - Hassan Anwar; Syed M. A. H. Jafri; Sergei Dytckov; Masoud Daneshtalab; Masoumeh Ebrahimi; Ahmed Hemani; Juha Plosila; Giovanni Beltrame; Hannu Tenhunen (MES, 2014)

A many-core hardware acceleration platform for short read mapping problem using distributed memory interface with 3D-stacked architecture. - Pei Liu 003; Ahmed Hemani; Kolin Paul (ISSoC, 2014)

Customization methodology of a Coarse Grained Reconfigurable architecture. - Siavoosh Payandeh Azad; Nasim Farahini; Ahmed Hemani (NORCHIP, 2014)

RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAs. - Syed M. A. H. Jafri; Guilermo Serrano; Junaid Iqbal; Masoud Daneshtalab; Ahmed Hemani; Kolin Paul; Juha Plosila; Hannu Tenhunen (ICSAMOS, 2014)

Private reliability environments for efficient fault-tolerance in CGRAs. - Syed M. A. H. Jafri; Stanislaw J. Piestrak; Ahmed Hemani; Kolin Paul; Juha Plosila; Hannu Tenhunen (Des. Autom. Embed. Syst., 2014)

Special issue on many-core embedded systems. - Masoud Daneshtalab; Maurizio Palesi; Juha Plosila; Ahmed Hemani (Microprocess. Microsystems, 2014)

Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric. - Nasim Farahini; Ahmed Hemani; Hasan Sohofi; Syed M. A. H. Jafri; Muhammad Adeel Tajammul; Kolin Paul (Microprocess. Microsystems, 2014)

Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains. - Jean-Michel Chabloz; Ahmed Hemani (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Atomic stream computation unit based on micro-thread level parallelism. - Nasim Farahini; Ahmed Hemani (ASAP, 2015)

FIST: A Framework to Interleave Spiking Neural Networks on CGRAs. - Tuan Ngyen; Syed M. A. H. Jafri; Masoud Daneshtalab; Ahmed Hemani; Sergei Dytckov; Juha Plosila; Hannu Tenhunen (PDP, 2015)

Physical design aware system level synthesis of hardware. - Nasim Farahini; Ahmed Hemani; Hasan Sohofi; Shuo Li 002 (SAMOS, 2015)

3D-stacked many-core architecture for biological sequence analysis problems. - Pei Liu 003; Ahmed Hemani; Kolin Paul (SAMOS, 2015)

DyMeP: An Infrastructure to Support Dynamic Memory Binding for Runtime Mapping in CGRAs. - Muhammad Adeel Tajammul; Syed M. A. H. Jafri; Peeter Ellervee; Ahmed Hemani; Hannu Tenhunen; Juha Plosila (VLSID, 2015)

Architecture and Implementation of Dynamic Parallelism, Voltage and Frequency Scaling (PVFS) on CGRAs. - Syed M. A. H. Jafri; Ozan Ozbag; Nasim Farahini; Kolin Paul; Ahmed Hemani; Juha Plosila; Hannu Tenhunen (ACM J. Emerg. Technol. Comput. Syst., 2015)

TEA: Timing and Energy Aware compression architecture for Efficient Configuration in CGRAs. - Syed M. A. H. Jafri; Masoud Daneshtalab; Ahmed Hemani; Naeem Abbas; Muhammad Ali Awan; Juha Plosila (Microprocess. Microsystems, 2015)

Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI. - Jamshaid Sarwar Malik; Ahmed Hemani; Jameel Nawaz Malik; Ben Slimane; Nasirud Din Gohar (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Elastic Management and QoS Provisioning Scheme for Adaptable Multi-core Protocol Processing Architecture. - Mohammad Badawi; Zhonghai Lu; Ahmed Hemani (DSD, 2016)

The SiLago Method: Next Generation VLSI Architectures and Design Methods. - Ahmed Hemani (MES@ISCA, 2016)

TransMem: A memory architecture to support dynamic remapping and parallelism in low power high performance CGRAs. - Muhammad Adeel Tajammul; Syed M. A. H. Jafri; Ahmed Hemani; Peeter Ellervee (PATMOS, 2016)

Service-Guaranteed Multi-port Packet Memory for Parallel Protocol Processing Architecture. - Mohammad Badawi; Zhonghai Lu; Ahmed Hemani (PDP, 2016)

Gaussian Random Number Generation: A Survey on Hardware Architectures. - Jamshaid Sarwar Malik; Ahmed Hemani (ACM Comput. Surv., 2016)

TransMap: Transformation Based Remapping and Parallelism for High Utilization and Energy Efficiency in CGRAs. - Syed M. A. H. Jafri; Masoud Daneshtalab; Naeem Abbas; Guillermo Serrano Leon; Ahmed Hemani (IEEE Trans. Computers, 2016)

Polymorphic Configuration Architecture for CGRAs. - Syed Mohammad Asad Hassan Jafri; Muhammad Adeel Tajammul; Ahmed Hemani; Kolin Paul; Juha Plosila; Peeter Ellervee; Hannu Tenhunen (IEEE Trans. Very Large Scale Integr. Syst., 2016)

SPEED: Open-Source Framework to Accelerate Speech Recognition on Embedded GPUs. - Syed Mohammad Asad Hassan Jafri; Ahmed Hemani; Leonardo Intesa (DSD, 2017)

MTP-Caffe: Memory, Timing, and Power aware tool for mapping CNNs to GPUs. - Yu Yang; Syed M. A. H. Jafri; Ahmed Hemani; Dimitrios Stathis 001 (PARMA-DITAM@HiPEAC, 2017)

MOCHA: Morphable Locality and Compression Aware Architecture for Convolutional Neural Networks. - Syed Mohammad Asad Hassan Jafri; Ahmed Hemani; Kolin Paul; Naeem Abbas (IPDPS, 2017)

SiLago-CoG: Coarse-Grained Grid-Based Design for Near Tape-Out Power Estimation Accuracy at High Level. - Syed Mohammad Asad Hassan Jafri; Nasim Farahini; Ahmed Hemani (ISVLSI, 2017)

Synchoricity and NOCs could make Billion Gate Custom Hardware Centric SOCs Affordable. - Ahmed Hemani; Syed Mohammad Asad Hassan Jafri; Shayesteh Masoumian (NOCS, 2017)

Can a reconfigurable architecture beat ASIC as a CNN accelerator? - Syed M. A. H. Jafri; Ahmed Hemani; Dimitrios Stathis 001 (SAMOS, 2017)

3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems. - Pei Liu 003; Ahmed Hemani; Kolin Paul; Christian Weis; Matthias Jung 001; Norbert Wehn (Int. J. Parallel Program., 2017)

Quality-of-service-aware adaptation scheme for multi-core protocol processing architecture. - Mohammad Badawi; Zhonghai Lu; Ahmed Hemani (Microprocess. Microsystems, 2017)

A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D-Stacked Architecture. - Pei Liu 003; Ahmed Hemani; Kolin Paul; Christian Weis; Matthias Jung 001; Norbert Wehn (J. Signal Process. Syst., 2017)

RiBoSOM: rapid bacterial genome identification using self-organizing map implemented on the synchoros SiLago platform. - Yu Yang; Dimitrios Stathis 001; Prashant Sharma; Kolin Paul; Ahmed Hemani; Manfred G. Grabherr; Rafi Ahmad (SAMOS, 2018)

Approximate Computing Applied to Bacterial Genome Identification using Self-Organizing Maps. - Dimitrios Stathis 001; Yu Yang; Saurabh Tewari; Ahmed Hemani; Kolin Paul; Manfred G. Grabherr; Rafi Ahmad (ISVLSI, 2019)

Regional Clock Tree Generation by Abutment in Synchoros VLSI Design. - Dimitrios Stathis 001; Panagiotis Chaourani; Syed M. A. H. Jafri; Ahmed Hemani (CoRR, 2019)

eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex. - Dimitrios Stathis 001; Chirag Sudarshan; Yu Yang; Matthias Jung 001; Syed Mohammad Asad Hassan Jafri; Christian Weis; Ahmed Hemani; Anders Lansner; Norbert Wehn (CoRR, 2019)

Configurable FFT Processor Using Dynamically Reconfigurable Resource Arrays. - Muhammad Ali Shami; Muhammad Adeel Tajammul; Ahmed Hemani (J. Signal Process. Syst., 2019)

NACU: A Non-Linear Arithmetic Unit for Neural Networks. - Guido Baccelli; Dimitrios Stathis 001; Ahmed Hemani; Maurizio Martina (DAC, 2020)

A FPGA-based Hardware Accelerator for Bayesian Confidence Propagation Neural Network. - Lizheng Liu; Deyu Wang; Yuning Wang; Anders Lansner; Ahmed Hemani; Yu Yang; Xiaoming Hu 001; Zhuo Zou; Lirong Zheng 001 (NorCAS, 2020)

Guest Editorial: Special Issue on Architectures and Design Methods for Neural Networks. - Ahmed Hemani; Muhammad Shafique 001; Kolin Paul (J. Signal Process. Syst., 2020)

eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex. - Dimitrios Stathis 001; Chirag Sudarshan; Yu Yang; Matthias Jung 001; Christian Weis; Ahmed Hemani; Anders Lansner; Norbert Wehn (J. Signal Process. Syst., 2020)

A Memristor Model with Concise Window Function for Spiking Brain-Inspired Computation. - Jiawei Xu 002; Deyu Wang; Feng Li 051; Lianhao Zhang; Dimitrios Stathis 001; Yu Yang; Yi Jin 007; Anders Lansner; Ahmed Hemani; Zhuo Zou; Li-Rong Zheng 001 (AICAS, 2021)

Approximate computation of post-synaptic spikes reduces bandwidth to synaptic storage in a model of cortex. - Dimitrios Stathis 001; Yu Yang; Ahmed Hemani; Anders Lansner (DATE, 2021)

Scheduling Persistent and Fully Cooperative Instructions. - Yu Yang; Ahmed Hemani; Kolin Paul (FCCM, 2021)

Synthesis of predictable global NoC by abutment in synchoros VLSI design. - Jordi Altayó González; Dimitrios Stathis 001; Ahmed Hemani (NOCS, 2021)

Design and Implementation of Optimized Register File for Streaming Applications. - Ayazulla Khan Patan; Dimitrios Stathis 001; Pudi Dhilleswararao; Yu Yang; Srinivas Boppu; Ahmed Hemani (VDAT, 2021)

Multi-objective Recurrent Neural Networks Optimization for the Edge - a Quantization-based Approach. - Nesma M. Rezk; Tomas Nordström; Dimitrios Stathis 001; Zain Ul-Abdin; Eren Erdal Aksoy; Ahmed Hemani (CoRR, 2021)

Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators. - Syed Mohammad Asad Hassan Jafri; Hasan Hassan; Ahmed Hemani; Onur Mutlu (ACM Trans. Archit. Code Optim., 2021)

Memristor-Based In-Circuit Computation for Trace-Based STDP. - Deyu Wang; Jiawei Xu 002; Feng Li 051; Lianhao Zhang; Yuning Wang; Anders Lansner; Ahmed Hemani; Lirong Zheng 001; Zhuo Zou (AICAS, 2022)

Reducing the Configuration Overhead of the Distributed Two-level Control System. - Yu Yang; Dimitrios Stathis 001; Ahmed Hemani (DATE, 2022)

Vesyla-II: An Algorithm Library Development Tool for Synchoros VLSI Design Style. - Yu Yang; Ahmed Hemani (CoRR, 2022)

MOHAQ: Multi-Objective Hardware-Aware Quantization of recurrent neural networks. - Nesma M. Rezk; Tomas Nordström; Dimitrios Stathis 001; Zain Ul-Abdin; Eren Erdal Aksoy; Ahmed Hemani (J. Syst. Archit., 2022)

Implementation of Sobel Edge Detection on DRRA and DiMArch Architectures. - Pudi Dhilleswararao; Rajeev Ryansh; Vamsi Goudu; Srinivas Boppu; Ahmed Hemani (DSD, 2023)

Efficient Implementation of 2-D Convolution on DRRA and DiMArch Architectures. - Pudi Dhilleswararao; Rajeev Ryansh; Srinivas Boppu; Yu Yang; Ahmed Hemani (HEART, 2023)

Optimizing Self-Organizing Maps for Bacterial Genome Identification on Parallel Ultra-Low-Power Platforms. - Seyed Ahmad Mirsalari; Saba Yousefzadeh; Giuseppe Tagliavini; Dimitrios Stathis 001; Ahmed Hemani (ICECS, 2023)

Optoelectronic Memristor Model for Optical Synaptic Circuit of Spiking Neural Networks. - Jiawei Xu 002; Yi Zheng; Chenxu Sheng; Yichen Cai 003; Dimitrios Stathis 001; Ruisi Shen; Lirong Zheng 001; Zhuo Zou; Laigui Hu; Ahmed Hemani (NEWCAS, 2023)

Implementation of Image Averaging on DRRA and DiMArch Architectures. - Pudi Dhilleswararao; Vamsi Goudu; Srinivas Boppu; Ritika Ratnu; Ahmed Hemani (SBCCI, 2023)

DRRA-based Reconfigurable Architecture for Mixed-Radix FFT. - Reeshita Kallapu; Dimitrios Stathis 001; Srinivas Boppu; Ahmed Hemani (VLSID, 2023)

Clock tree generation by abutment in synchoros VLSI design. - Dimitrios Stathis 001; Panagiotis Chaourani; Syed M. A. H. Jafri; Ahmed Hemani (Microprocess. Microsystems, 2023)

A Memristor-Based Learning Engine for Synaptic Trace-Based Online Learning. - Deyu Wang; Jiawei Xu 002; Feng Li 051; Lianhao Zhang; Chengwei Cao; Dimitrios Stathis 001; Anders Lansner; Ahmed Hemani; Lirong Zheng 001; Zhuo Zou (IEEE Trans. Biomed. Circuits Syst., 2023)

FPGA-Based HPC for Associative Memory System. - Deyu Wang; Yuning Wang; Yu Yang; Dimitrios Stathis 001; Ahmed Hemani; Anders Lansner; Jiawei Xu 002; Li-Rong Zheng 001; Zhuo Zou (ASPDAC, 2024)

Exploration of Custom Floating-Point Formats: A Systematic Approach. - Saba Yousefzadeh; Yu Yang; Astile Peter; Dimitrios Stathis 001; Ahmed Hemani (DSD, 2024)

Integer Linear Programming-Based Simultaneous Scheduling and Binding for SiLago Framework. - Pudi Dhilleswararao; Shivam Malviya; Srinivas Boppu; Yu Yang; Ahmed Hemani; Linga Reddy Cenkeramaddi (IEEE Access, 2024)

Application Level Synthesis: Creating Matrix-Matrix Multiplication Library: A Case Study. - Pudi Dhilleswararao; Yu Yang; Dimitrios Stathis 001; Sunil Kumar Prajapati; Srinivas Boppu; Ahmed Hemani; Linga Reddy Cenkeramaddi (IEEE Access, 2024)

CIS: Composable Instruction Set for Streaming Applications: Design, Modeling, and Scheduling. - Yu Yang; Jordi Altayó González; Ahmed Hemani (CoRR, 2024)

DUDE: Decryption, Unpacking, Deobfuscation, and Endian Conversion Framework for Embedded Devices Firmware. - Haider Abbas; Muhammad Shahzad; Maliha Safdar; Ahmed Hemani (IEEE Trans. Dependable Secur. Comput., 2024)

Modeling Cycle-to-Cycle Variation in Memristors for In-Situ Unsupervised Trace-STDP Learning. - Jiawei Xu 002; Yi Zheng; Feng Li 051; Dimitrios Stathis 001; Ruisi Shen; Haoming Chu; Anders Lansner; Lirong Zheng 001; Zhuo Zou; Ahmed Hemani (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Automating functional unit and register binding for synchoros CGRA platform. - Pudi Dhilleswararao; Utsav Tiwari; Srinivas Boppu; Yu Yang; Ahmed Hemani (Des. Autom. Embed. Syst., 2024)

Scalable Multi-FPGA HPC Architecture for Associative Memory System. - Deyu Wang; Xiaoze Yan; Yu Yang; Dimitrios Stathis 001; Ahmed Hemani; Anders Lansner; Jiawei Xu 002; Li-Rong Zheng 001; Zhuo Zou (IEEE Trans. Biomed. Circuits Syst., 2025)