A Parallel Architecture for Optical Computing. - Ahmed Louri; Kai Hwang 001 (PP, 1987)

Optical Arithmetic Using Signed-Digit Symbolic Substitution. - Kai Hwang 001; Ahmed Louri (ICPP (1), 1988)

A Bit-Plane Architecture for Optical Computing with Two-Dimensional Symbolic Substitution. - Ahmed Louri; Kai Hwang 001 (ISCA, 1988)

A Symbolic Substitution Based Parallel Architecture and Algorithms for High-speed Parallel Processing. - Ahmed Louri (ACM Conference on Computer Science, 1990)

Design and Evaluation of Fault-Tolerant Interleaved Memory Systems. - Sy-Yen Kuo; Ahmed Louri; Sheng-Chiech Liang (ICPP (1), 1991)

Design of an Optical Content-Addressable Parallel Processor with Applications to Fast Searching and Information Retrieval. - Ahmed Louri (IPPS, 1991)

An Optical Content-Adressable Parallel Processor for Fast Searching and Retrieving. - Ahmed Louri (PARLE (1), 1991)

Three-dimensional optical architecture and data-parallel algorithms for massively parallel computing. - Ahmed Louri (IEEE Micro, 1991)

A Compiler Directed Cache Coherence Scheme with Fast and Parallel Explicit Invalidation. - Ahmed Louri; Hongki Sung (ICPP (1), 1992)

Parallel electro-optical rule-based system for fast execution of expert systems. - Ahmed Louri; Jongwhoa Na (ISCA, 1992)

A new compiler-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation. - Ahmed Louri; Hongki Sung (ISCA, 1992)

Performance Considerations Relating to the Design of Interconnection Networks for Multiprocessing Systems. - Earl Hokens; Ahmed Louri (ICPP (1), 1993)

A Simulation Environment for Intelligent Machine Architectures. - Bernard P. Zeigler; Ahmed Louri (J. Parallel Distributed Comput., 1993)

An Optical Associative Parallel Processor for High-Speed Database Processing. - Ahmed Louri; James A. Hatch Jr. (Computer, 1994)

3D Optical Interconnects for High-Speed Interchip and Interboard Communications. - Ahmed Louri; Hongki Sung (Computer, 1994)

A constant-time parallel sorting algorithm and its optical implementation. - Ahmed Louri; James A. Hatch Jr.; Jongwhoa Na (IEEE Micro, 1995)

Media Access Protocols For A Scalable Optical Interconnection Network. - Thomas S. Jones; Ahmed Louri (ICPP, 1998)

A Spanning Multichannel Linked Hypercube: A Gradually Scalable Optical Interconnection Network for Massively Parallel Computing. - Ahmed Louri; Brent Weech; Costas Neocleous (IEEE Trans. Parallel Distributed Syst., 1998)

A Multi-Wavelength Optical Content-Addressable Parallel Processor (MW-OCAPP) for High-Speed Parallel Relational Database Processing: Architectural Concepts and Preliminary Experimental System. - Peng Yin Choo; Abram Detofsky; Ahmed Louri (IPPS/SPDP Workshops, 1999)

The Equivalency Processing Parallel Photonic Integrated Circuit (EP3IC), a Parallel Digital Equivalence Search Module. - Peng Yin Choo; Abram Detofsky; Ahmed Louri (AIPR, 2000)

A Class of Highly Scalable Optical Crossbar-Connected Interconnection Networks (SOCNs) for Parallel Computing Systems. - Brian Webb; Ahmed Louri (IEEE Trans. Parallel Distributed Syst., 2000)

A Scalable Architecture for Distributed Shared Memory Multiprocessors Using Optical Interconnects. - Avinash Karanth Kodi; Ahmed Louri (IPDPS, 2004)

An Optical Interconnection Network and a Modified Snooping Protocol for the Design of Large-Scale Symmetric Multiprocessors (SMPs). - Ahmed Louri; Avinash Karanth Kodi (IEEE Trans. Parallel Distributed Syst., 2004)

Design of a High-Speed Optical Interconnect for Scalable Shared-Memory Multiprocessors. - Avinash Karanth Kodi; Ahmed Louri (IEEE Micro, 2005)

A New Dynamic Bandwidth Re-Allocation Technique in Optically Interconnected High-Performance Computing Systems. - Avinash Karanth Kodi; Ahmed Louri (Hot Interconnects, 2006)

Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture. - Avinash Karanth Kodi; Ashwini Sarathy; Ahmed Louri (ANCS, 2007)

Implementation of Dynamic Bandwidth Re-allocation in Optical Interconnects using Microring Resonators. - Chander Kochar; Avinash Karanth Kodi; Ahmed Louri (Hot Interconnects, 2007)

Power-Aware Bandwidth-Reconfigurable Optical Interconnects for High-Performance Computing (HPC) Systems. - Avinash Karanth Kodi; Ahmed Louri (IPDPS, 2007)

Performance adaptive power-aware reconfigurable optical interconnects for high-performance computing (HPC) systems. - Avinash Karanth Kodi; Ahmed Louri (SC, 2007)

iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures. - Avinash Karanth Kodi; Ashwini Sarathy; Ahmed Louri (ISCA, 2008)

Optisim: A System Simulation Methodology for Optically Interconnected HPC Systems. - Avinash Karanth Kodi; Ahmed Louri (IEEE Micro, 2008)

Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis. - Avinash Karanth Kodi; Ashwini Sarathy; Ahmed Louri (IEEE Trans. Computers, 2008)

Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures. - Avinash Karanth Kodi; Ashwini Sarathy; Ahmed Louri; Janet Meiling Wang (ASP-DAC, 2009)

Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs). - Avinash Karanth Kodi; Ahmed Louri; Janet Meiling Wang (ISQED, 2009)

NBTI aware workload balancing in multi-core systems. - Jin Sun 006; Avinash Karanth Kodi; Ahmed Louri; Janet Meiling Wang (ISQED, 2009)

On-Chip photonic interconnects for scalable multi-core architectures. - Avinash Karanth Kodi; Randy Morris; Ahmed Louri; Xiang Zhang (NOCS, 2009)

Workload capacity considering NBTI degradation in multi-core systems. - Jin Sun 006; Roman L. Lysecky; Karthik Shankar; Avinash Karanth Kodi; Ahmed Louri; Janet Meiling Wang (ASP-DAC, 2010)

A multilayer nanophotonic interconnection network for on-chip many-core communications. - Xiang Zhang; Ahmed Louri (DAC, 2010)

Special Issue on Network-on-Chips (NoCs). - Ahmed Louri; Avinash Karanth Kodi (J. Parallel Distributed Comput., 2010)

Co-design of channel buffers and crossbar organizations in NoCs architectures. - Avinash Karanth Kodi; Randy Morris; Dominic DiTomaso; Ashwini Sarathy; Ahmed Louri (ICCAD, 2011)

ROBUST: a new self-healing fault-tolerant NoC router. - Jacques Henri Collet; Ahmed Louri; Vivek Tulsidas Bhat; Pavan Poluri (NoCArc@MICRO, 2011)

Introduction to the special issue on Networks-on-Chip (NoC) of the Journal of Parallel and Distributed Computing (JPDC). - Ahmed Louri; Avinash Karanth Kodi (J. Parallel Distributed Comput., 2011)

3D-NoC: Reconfigurable 3D photonic on-chip interconnect for multicores. - Randy Morris; Avinash Karanth Kodi; Ahmed Louri (ICCD, 2012)

Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance. - Randy Morris; Avinash Karanth Kodi; Ahmed Louri (MICRO, 2012)

Evaluation of fault tolerant channel buffers for improving reliability in NoCs. - Dominic DiTomaso; Travis Boraten; Avinash Kodi; Ahmed Louri (MWSCAS, 2012)

Design of a Concentrated Torus Topology with Channel Buffers and Efficient Crossbars in NoCs. - Dominic DiTomaso; Randy Morris; Evan Jolley; Ashwini Sarathy; Ahmed Louri; Avinash Karanth Kodi (IPDPS Workshops, 2013)

Tackling Permanent Faults in the Network-on-Chip Router Pipeline. - Pavan Poluri; Ahmed Louri (SBAC-PAD, 2013)

Evaluating the scalability and performance of 3D stacked reconfigurable nanophotonic interconnects. - Randy Morris; Avinash Karanth Kodi; Ahmed Louri (SLIP, 2013)

Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips. - Dominic DiTomaso; Randy Morris; Avinash Karanth Kodi; Ashwini Sarathy; Ahmed Louri (IEEE Trans. Very Large Scale Integr. Syst., 2013)

QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers. - Dominic DiTomaso; Avinash Karanth Kodi; Ahmed Louri (HPCA, 2014)

An Improved Router Design for Reliable On-Chip Networks. - Pavan Poluri; Ahmed Louri (IPDPS, 2014)

Workload assignment considering NBTI degradation in multicore systems. - Jin Sun 006; Roman L. Lysecky; Karthik Shankar; Avinash Karanth Kodi; Ahmed Louri; Janet Roveda (ACM J. Emerg. Technol. Comput. Syst., 2014)

Three-Dimensional Stacked Nanophotonic Network-on-Chip Architecture with Minimal Reconfiguration. - Randy Morris; Avinash Karanth Kodi; Ahmed Louri; Ralph D. Whaley (IEEE Trans. Computers, 2014)

OWN: Optical and Wireless Network-on-Chip for Kilo-core Architectures. - Md. Ashif I. Sikder; Avinash Karanth Kodi; Matthew Kennedy; Savas Kaya; Ahmed Louri (Hot Interconnects, 2015)

A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core Systems. - Pavan Poluri; Ahmed Louri (IEEE Comput. Archit. Lett., 2015)

Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures. - Dominic DiTomaso; Avinash Karanth Kodi; Ahmed Louri; Razvan C. Bunescu (IEEE Trans. Computers, 2015)

Dynamic error mitigation in NoCs using intelligent prediction techniques. - Dominic DiTomaso; Travis Boraten; Avinash Kodi; Ahmed Louri (MICRO, 2016)

Reconfigurable Optical and Wireless (R-OWN) Network-on-Chip for High Performance Computing. - Md. Ashif I. Sikder; Avinash Karanth Kodi; Ahmed Louri (NANOCOM, 2016)

Design of high bandwidth photonic NoC architectures using optical multilevel signaling. - Tzyy-Juin Kao; Ahmed Louri (NOCS, 2016)

A Methodology for Cognitive NoC Design. - Wo-Tak Wu; Ahmed Louri (IEEE Comput. Archit. Lett., 2016)

Shield: A Reliable Network-on-Chip Router Architecture for Chip Multiprocessors. - Pavan Poluri; Ahmed Louri (IEEE Trans. Parallel Distributed Syst., 2016)

Machine learning enabled power-aware Network-on-Chip design. - Dominic DiTomaso; Md. Ashif I. Sikder; Avinash Karanth Kodi; Ahmed Louri (DATE, 2017)

Ultra-compact sub-10nm logic circuits based on ambipolar SB-FinFETs. - Talha Furkan Canan; Savas Kaya; Avinash Kodi; Hao Xin; Ahmed Louri (MWSCAS, 2017)

LEAD: learning-enabled energy-aware dynamic voltage/frequency scaling in NoCs. - Mark Clark; Avinash Kodi; Razvan C. Bunescu; Ahmed Louri (DAC, 2018)

Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning. - Scott Van Winkle; Avinash Karanth Kodi; Razvan C. Bunescu; Ahmed Louri (HPCA, 2018)

DEC-NoC: An Approximate Framework Based on Dynamic Error Control with Applications to Energy-Efficient NoCs. - Yuechen Chen; Md Farhadur Reza; Ahmed Louri (ICCD, 2018)

10T and 8T Full Adders Based on Ambipolar XOR Gates with SB-FinFETs. - Talha Furkan Canan; Savas Kaya; Avinash Kodi; Hao Xin; Ahmed Louri (ICECS, 2018)

Scalable Power-Efficient Kilo-Core Photonic-Wireless NoC Architectures. - Avinash Kodi; Kyle Shifflet; Savas Kaya; Soumyasanta Laha; Ahmed Louri (IPDPS, 2018)

Sub-THz Tunable Push-Push Oscillators with FinFETs for Wireless NoCs. - Yunus Kelestemur; Soumyasanta Laha; Savas Kaya; Avinash Kodi; Hao Xin; Ahmed Louri (MWSCAS, 2018)

EZ-Pass: An Energy & Performance-Efficient Power-Gating Router Architecture for Scalable NoCs. - Hao Zheng 005; Ahmed Louri (IEEE Comput. Archit. Lett., 2018)

An Energy-Efficient Network-on-Chip Design using Reinforcement Learning. - Hao Zheng 005; Ahmed Louri (DAC, 2019)

High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learnin. - Ke Wang 030; Ahmed Louri; Avinash Karanth; Razvan C. Bunescu (DATE, 2019)

An online quality management framework for approximate communication in network-on-chips. - Yuechen Chen; Ahmed Louri (ICS, 2019)

IntelliNoC: a holistic design framework for energy-efficient and reliable on-chip communication for manycores. - Ke Wang 030; Ahmed Louri; Avinash Karanth; Razvan C. Bunescu (ISCA, 2019)

Limit of Hardware Solutions for Self-Protecting Fault-Tolerant NoCs. - Ahmed Louri; Jacques Henri Collet; Avinash Karanth (ACM J. Emerg. Technol. Comput. Syst., 2019)

Utility-based resource management in an oversubscribed energy-constrained heterogeneous environment executing parallel applications. - Dylan Machovec; Bhavesh Khemka; Nirmal Kumbhare; Sudeep Pasricha; Anthony A. Maciejewski; Howard Jay Siegel; Ali Akoglu; Gregory A. Koenig; Salim Hariri; Cihan Tunc; Michael Wright; Marcia Hilton; et al. (Parallel Comput., 2019)

Dynamic Voltage and Frequency Scaling in NoCs with Supervised and Reinforcement Learning Techniques. - Quintin Fettes; Mark Clark; Razvan C. Bunescu; Avinash Karanth; Ahmed Louri (IEEE Trans. Computers, 2019)

Editorial from the Incoming Editor-in-Chief. - Ahmed Louri (IEEE Trans. Computers, 2019)

Sustainability in Network-on-Chips by Exploring Heterogeneity in Emerging Technologies. - Avinash Karanth; Savas Kaya; Md. Ashif I. Sikder; Daniel Carbaugh; Soumyasanta Laha; Dominic DiTomaso; Ahmed Louri; Hao Xin; JunQiang Wu (IEEE Trans. Sustain. Comput., 2019)

A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures. - Hao Zheng 005; Ke Wang 030; Ahmed Louri (DAC, 2020)

PIXEL: Photonic Neural Network Accelerator. - Kyle Shiflett; Dylan Wright; Avinash Karanth; Ahmed Louri (HPCA, 2020)

4-Input NAND and NOR Gates Based on Two Ambipolar Schottky Barrier FinFETs. - Talha Furkan Canan; Savas Kaya; Avinash Karanth; Ahmed Louri (ICECS, 2020)

DozzNoC: Reducing Static and Dynamic Energy in NoCs with Low-latency Voltage Regulators using Machine Learning. - Mark Clark; Yingping Chen; Avinash Karanth; Dongsheng Brian Ma; Ahmed Louri (IPDPS, 2020)

TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-on-Chip Architecture. - Ke Wang 030; Hao Zheng 005; Ahmed Louri (IEEE Micro, 2020)

State of the Journal. - Ahmed Louri (IEEE Trans. Computers, 2020)

Learning-Based Quality Management for Approximate Communication in Network-on-Chips. - Yuechen Chen; Ahmed Louri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Hardware-Level Thread Migration to Reduce On-Chip Data Movement Via Reinforcement Learning. - Quintin Fettes; Avinash Karanth; Razvan C. Bunescu; Ahmed Louri; Kyle Shiflett (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

An Approximate Communication Framework for Network-on-Chips. - Yuechen Chen; Ahmed Louri (IEEE Trans. Parallel Distributed Syst., 2020)

CURE: A High-Performance, Low-Power, and Reliable Network-on-Chip Design Using Reinforcement Learning. - Ke Wang 030; Ahmed Louri (IEEE Trans. Parallel Distributed Syst., 2020)

Scaling Deep-Learning Inference with Chiplet-based Architecture and Photonic Interconnects. - Yuan Li 029; Ahmed Louri; Avinash Karanth (DAC, 2021)

Bitwise Neural Network Acceleration Using Silicon Photonics. - Kyle Shiflett; Avinash Karanth; Ahmed Louri; Razvan C. Bunescu (ACM Great Lakes Symposium on VLSI, 2021)

Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures. - Hao Zheng 005; Ke Wang 030; Ahmed Louri (HPCA, 2021)

CSCNN: Algorithm-hardware Co-design for CNN Accelerators using Centrosymmetric Filters. - Jiajun Li; Ahmed Louri; Avinash Karanth; Razvan C. Bunescu (HPCA, 2021)

GCNAX: A Flexible and Energy-efficient Accelerator for Graph Convolutional Neural Networks. - Jiajun Li; Ahmed Louri; Avinash Karanth; Razvan C. Bunescu (HPCA, 2021)

Albireo: Energy-Efficient Acceleration of Convolutional Neural Networks via Silicon Photonics. - Kyle Shiflett; Avinash Karanth; Razvan C. Bunescu; Ahmed Louri (ISCA, 2021)

Stochastic Dividers for Low Latency Neural Networks. - Shanshan Liu 001; Xiaochen Tang; Farzad Niknia; Pedro Reviriego; Weiqiang Liu 001; Ahmed Louri; Fabrizio Lombardi (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Reduced Precision Redundancy for Reliable Processing of Data. - Shanshan Liu 001; Ke Chen 018; Pedro Reviriego; Weiqiang Liu 001; Ahmed Louri; Fabrizio Lombardi (IEEE Trans. Emerg. Top. Comput., 2021)

ALPHA: A Learning-Enabled High-Performance Network-on-Chip Router Design for Heterogeneous Manycore Architectures. - Yuan Li 029; Ahmed Louri (IEEE Trans. Sustain. Comput., 2021)

AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems. - Ke Wang 030; Hao Zheng 005; Yuan Li 029; Jiajun Li; Ahmed Louri (DATE, 2022)

Adapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous Dataflow Implementation. - Jiaqi Yang; Hao Zheng 005; Ahmed Louri (ACM Great Lakes Symposium on VLSI, 2022)

SPACX: Silicon Photonics-based Scalable Chiplet Accelerator for DNN Inference. - Yuan Li 029; Ahmed Louri; Avinash Karanth (HPCA, 2022)

FSA: An Efficient Fault-tolerant Systolic Array-based DNN Accelerator Architecture. - Yingnan Zhao 001; Ke Wang 030; Ahmed Louri (ICCD, 2022)

Approximate Network-on-Chips with Application to Image Classification. - Yuechen Chen; Ahmed Louri; Shanshan Liu 001; Fabrizio Lombardi (NAS, 2022)

Ascend: A Scalable and Energy-Efficient Deep Neural Network Accelerator With Photonic Interconnects. - Yuan Li 029; Ke Wang 030; Hao Zheng 005; Ahmed Louri; Avinash Karanth (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Delta Sigma Modulator-Based Stochastic Divider. - Xiaochen Tang; Shanshan Liu 001; Farzad Niknia; Pedro Reviriego; Ziheng Wang; Wei Tang 002; Ahmed Louri; Fabrizio Lombardi (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Agile: A Learning-Enabled Power and Performance-Efficient Network-on-Chip Design. - Hao Zheng 005; Ahmed Louri (IEEE Trans. Emerg. Top. Comput., 2022)

SPRINT: A High-Performance, Energy-Efficient, and Scalable Chiplet-Based Accelerator With Photonic Interconnects for CNN Inference. - Yuan Li 029; Ahmed Louri; Avinash Karanth (IEEE Trans. Parallel Distributed Syst., 2022)

SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator With Workload Balancing. - Jiajun Li; Hao Zheng 005; Ke Wang 030; Ahmed Louri (IEEE Trans. Parallel Distributed Syst., 2022)

AdaPrune: An Accelerator-Aware Pruning Technique for Sustainable CNN Accelerators. - Jiajun Li; Ahmed Louri (IEEE Trans. Sustain. Comput., 2022)

SecureNoC: A Learning-Enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework Design. - Ke Wang 030; Hao Zheng 005; Yuan Li 029; Ahmed Louri (IEEE Trans. Sustain. Comput., 2022)

A Silicon Photonic Multi-DNN Accelerator. - Yuan Li 029; Ahmed Louri; Avinash Karanth (PACT, 2023)

Venus: A Versatile Deep Neural Network Accelerator Architecture Design for Multiple Applications. - Jiaqi Yang; Hao Zheng 005; Ahmed Louri (DAC, 2023)

ARIES: Accelerating Distributed Training in Chiplet-Based Systems via Flexible Interconnects. - Lingxiang Yin; Amir Ghazizadeh; Ahmed Louri; Hao Zheng 005 (ICCAD, 2023)

Polyform: A Versatile Architecture for Multi-DNN Execution via Spatial and Temporal Acceleration. - Lingxiang Yin; Amir Ghazizadeh; Shilin Tian; Ahmed Louri; Hao Zheng 005 (ICCD, 2023)

Flumen: Dynamic Processing in the Photonic Interconnect. - Kyle Shiflett; Avinash Karanth; Razvan C. Bunescu; Ahmed Louri (ISCA, 2023)

A Technique for Approximate Communication in Network-on-Chips for Image Classification. - Yuechen Chen; Shanshan Liu 001; Fabrizio Lombardi; Ahmed Louri (IEEE Trans. Emerg. Top. Comput., 2023)

Slack-Aware Packet Approximation for Energy-Efficient Network-on-Chips. - Yuechen Chen; Ahmed Louri; Shanshan Liu 001; Fabrizio Lombardi (IEEE Trans. Sustain. Comput., 2023)

GShuttle: Optimizing Memory Access Efficiency for Graph Convolutional Neural Network Accelerators. - Jiajun Li; Ke Wang 030; Hao Zheng 005; Ahmed Louri (J. Comput. Sci. Technol., 2023)

Error-Resilient Data Compression With Tunstall Codes. - Shanshan Liu 001; Pedro Reviriego; Anees Ullah; Ahmed Louri; Fabrizio Lombardi (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

VITA: ViT Acceleration for Efficient 3D Human Mesh Recovery via Hardware-Algorithm Co-Design. - Shilin Tian; Chase Szafranski; Ce Zheng; Fan Yao; Ahmed Louri; Chen Chen 001; Hao Zheng 005 (DAC, 2024)

An Efficient Hardware Accelerator Design for Dynamic Graph Convolutional Network (DGCN) Inference. - Yingnan Zhao 001; Ke Wang 030; Jiaqi Yang; Ahmed Louri (DAC, 2024)

PCM Enabled Low-Power Photonic Accelerator for Inference and Training on Edge Devices. - Juliana Curry; Ahmed Louri; Avinash Karanth; Razvan C. Bunescu (IPDPS (Workshops), 2024)

Aurora: A Versatile and Flexible Accelerator for Graph Neural Networks. - Jiaqi Yang; Hao Zheng 005; Ahmed Louri (IPDPS, 2024)

Algorithmic Strategies for Sustainable Reuse of Neural Network Accelerators with Permanent Faults. - Youssef A. Ait Alama; Sampada Sakpal; Ke Wang 030; Razvan C. Bunescu; Avinash Karanth; Ahmed Louri (CoRR, 2024)

Morph-GCNX: A Universal Architecture for High-Performance and Energy-Efficient Graph Convolutional Network Acceleration. - Ke Wang 030; Hao Zheng 005; Jiajun Li; Ahmed Louri (IEEE Trans. Sustain. Comput., 2024)

A High-Performance and Energy-Efficient Photonic Architecture for Multi-DNN Acceleration. - Yuan Li 029; Ahmed Louri; Avinash Karanth (IEEE Trans. Parallel Distributed Syst., 2024)

Versa-DNN: A Versatile Architecture Enabling High-Performance and Energy-Efficient Multi-DNN Acceleration. - Jiaqi Yang; Hao Zheng 005; Ahmed Louri (IEEE Trans. Parallel Distributed Syst., 2024)

A Balanced Sparse Matrix Convolution Accelerator for Efficient CNN Training. - Yuechen Chen; Ahmed Louri; Shanshan Liu 001; Fabrizio Lombardi (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

OPT-GCN: A Unified and Scalable Chiplet-Based Accelerator for High-Performance and Energy-Efficient GCN Computation. - Yingnan Zhao 001; Ke Wang 030; Ahmed Louri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A High-Performance and Flexible Accelerator for Dynamic Graph Convolutional Networks. - Yingnan Zhao 001; Ke Wang 030; Ahmed Louri (DATE, 2025)

I-DGNN: A Graph Dissimilarity-based Framework for Designing Scalable and Efficient DGNN Accelerators. - Jiaqi Yang; Hao Zheng 005; Ahmed Louri (HPCA, 2025)

DiTile-DGNN: An Efficient Accelerator for Distributed Dynamic Graph Neural Network Inference. - Jiaqi Yang; Hao Zheng 005; Ahmed Louri (ISCA, 2025)

MERIT: A Sustainable DNN Accelerator Design With Photonic Phase-Change Memory. - Yuan Li 029; Ahmed Louri; Avinash Karanth (IEEE Trans. Sustain. Comput., 2025)