A New Full Adder Cell for Low-Power Applications. - Ahmed M. Shams; Magdy A. Bayoumi (Great Lakes Symposium on VLSI, 1998)

Performance evaluation of 1-bit CMOS adder cells. - Ahmed M. Shams; Magdy A. Bayoumi (ISCAS (1), 1999)

A 108 Gbps, 1.5 GHz 1D-DCT Architecture. - Ahmed M. Shams; Magdy A. Bayoumi (ASAP, 2000)

A high-performance 1D-DCT architecture. - Ahmed M. Shams; Wendi Pan; Archana Chandanandan; Magdy A. Bayoumi (ISCAS, 2000)

Hybrid Mesh-Based/Block-Based Motion Compensation Architecture. - Ahmed M. Shams; Mohamed A. Elgamel; Magdy A. Bayoumi (Workshop on Digital and Computational Video, 2001)

Enhanced low power motion estimation VLSI architectures for video compression. - Mohamed A. Elgamel; Ahmed M. Shams; Xi Xueling; Magdy A. Bayoumi (ISCAS (4), 2001)

A Low Power High Performance Distributed DCT Architecture. - Ahmed M. Shams; Wendi Pan; Archana Chidanandan; Magdy A. Bayoumi (ISVLSI, 2002)

Performance analysis of low-power 1-bit CMOS full adder cells. - Ahmed M. Shams; Tarek Darwish; Magdy A. Bayoumi (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Low Power Full Search Block Matching Motion Estimation Vlsi Architectures. - Mohamed A. Elgamel; Magdy A. Bayoumi; Ahmed M. Shams; Bertrand Y. Zavidovique (J. Circuits Syst. Comput., 2004)

NEDA: a low-power high-performance DCT architecture. - Ahmed M. Shams; Archana Chidanandan; Wendi Pan; Magdy A. Bayoumi (IEEE Trans. Signal Process., 2006)