Costs and benefits of flexibility in spatial division circuit switched networks-on-chip. - Ahsen Ejaz; Axel Jantsch (NoCArc@MICRO, 2013)

FreewayNoC: A DDR NoC with Pipeline Bypassing. - Ahsen Ejaz; Vassilios Papaefstathiou; Ioannis Sourdis (NOCS, 2018)

DDRNoC: Dual Data-Rate Network-on-Chip. - Ahsen Ejaz; Vassilios Papaefstathiou; Ioannis Sourdis (ACM Trans. Archit. Code Optim., 2018)

HighwayNoC: Approaching Ideal NoC Performance With Dual Data Rate Routers. - Ahsen Ejaz; Vassilis Papaefstathiou; Ioannis Sourdis (IEEE/ACM Trans. Netw., 2021)

FastTrackNoC: A NoC with FastTrack Router Datapaths. - Ahsen Ejaz; Ioannis Sourdis (HPCA, 2022)

eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem. - Lluc Alvarez; Abraham Ruiz; Arnau Bigas-Soldevilla; Pavel Kuroedov; Alberto González 004; Hamsika Mahale; Noe Bustamante; Albert Aguilera; Francesco Minervini; Javier Salamero; Oscar Palomar; Vassilis Papaefstathiou; et al. (CF, 2023)

BZSim: Fast, Large-Scale Microarchitectural Simulation with Detailed Interconnect Modeling. - Panagiotis Strikos; Ahsen Ejaz; Ioannis Sourdis (ISPASS, 2024)

A Performance Analysis of Chiplet-Based Systems. - Neethu Bal Mallya; Panagiotis Strikos; Bhavishya Goel; Ahsen Ejaz; Ioannis Sourdis (DATE, 2025)