Reconstructing Big Semantic Similarity Networks. - Ai He; Shefali Sharma; Chun-Nan Hsu (TextGraphs@EMNLP, 2013)

Two-Way Graphic Password for Mobile User Authentication. - Ming Jiang; Ai He; Kuangyu Wang; Zhengyi Le (CSCloud, 2015)

A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS. - Liangxiao Tang; Weixin Gai; Linqi Shi; Xiao Xiang; Kai Sheng; Ai He (ISSCC, 2018)

Double-Comparison Settling Error Correction Scheme for Binary Scaled SAR ADCs. - Ai He; Weixin Gai; Yufan Feng; Zhongzhu Pu; Xiao Xiang (ISCAS, 2019)

An 8-12GHz 0.92° Phase Error Quadrature Clock Generator Based on Two-Stage Poly Phase Filter with Intermediate Point Compensation. - Xiao Xiang; Weixin Gai; Linqi Shi; Ai He; Kai Sheng (ISCAS, 2019)

An Adaptive DFE Using Pattern-Dependent Data-Level Reference in 28 nm CMOS Technology. - Ai He; Weixin Gai; Kai Sheng; Ninghuang Li (ASICON, 2021)

56 Gb/s PAM4 receiver with an overshoot compensation scheme in 28 nm CMOS technology. - Ai He; Weixin Gai; Bingyi Ye; Boyang Zhang; Kai Sheng; Yuanliang Li (Microelectron. J., 2021)

Equal-slope baud-rate CDR algorithm with optimized eye opening. - Xiao Xiang; Weixin Gai; Ai He; Hang Zhou; Dong Yanchi (Microelectron. J., 2021)

Shrinking Factor Dimension: A Reduced-Rank Approach. - Ai He; Dashan Huang; Jiaen Li; Guofu Zhou (Manag. Sci., 2023)

A two-stage slicer employing body biasing for 64-Gb/s PAM4 wireline receiver in 22-nm FDSOI technology. - Ai He; Binhong Li; Jianzhong Li; Xing Zhao; Jincai Guo; Jianping Wang; Xiangqian Zeng; Yun Wang; Tianchun Ye 001; Quan Xue (Microelectron. J., 2024)