A chip-to-chip clock-deskewing circuit for 3-D ICs. - Ai-Jia Chuang; Yu Lee; Ching-Yuan Yang (ISCAS, 2012)

A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links. - Ching-Yuan Yang; Miao-Shan Li; Ai-Jia Chuang (IEEE Trans. Very Large Scale Integr. Syst., 2021)