Design of a Radiation Hardened Latch for Low-Power Circuits. - Huaguo Liang; Zhi Wang; Zhengfeng Huang; Aibin Yan (ATS, 2014)

A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology. - Aibin Yan; Huaguo Liang; Zhengfeng Huang; Cuiyun Jiang; Maoxiang Yi (IEICE Trans. Electron., 2015)

Novel Low Cost and Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology. - Aibin Yan; Zhengfeng Huang; Xiangsheng Fang; Xiaolin Xu; Huaguo Liang (ATS, 2016)

An SEU resilient, SET filterable and cost effective latch in presence of PVT variations. - Aibin Yan; Huaguo Liang; Zhengfeng Huang; Cuiyun Jiang; Yiming Ouyang; Xuejun Li (Microelectron. Reliab., 2016)

HLDTL: High-performance, low-cost, and double node upset tolerant latch design. - Aibin Yan; Zhengfeng Huang; Maoxiang Yi; Jie Cui 004; Huaguo Liang (VTS, 2017)

A single event transient detector in SRAM-based FPGAs. - Xiumin Xu; Huaguo Liang; Zhengfeng Huang; Cuiyun Jiang; Yingchun Lu; Aibin Yan; Tianming Ni; Maoxiang Yi (IEICE Electron. Express, 2017)

A transient pulse dually filterable and online self-recoverable latch. - Aibin Yan; Huaguo Liang; Yingchun Lu; Zhengfeng Huang (IEICE Electron. Express, 2017)

Highly Robust Double Node Upset Resilient Hardened Latch Design. - Huaguo Liang; Xin Li; Zhengfeng Huang; Aibin Yan; Xiumin Xu (IEICE Trans. Electron., 2017)

A Region-Based Through-Silicon via Repair Method for Clustered Faults. - Tianming Ni; Huaguo Liang; Mu Nie; Xiumin Xu; Aibin Yan; Zhengfeng Huang (IEICE Trans. Electron., 2017)

Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS. - Aibin Yan; Zhengfeng Huang; Xiangsheng Fang; Yiming Ouyang; Honghui Deng (Microelectron. J., 2017)

Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology. - Aibin Yan; Zhengfeng Huang; Maoxiang Yi; Xiumin Xu; Yiming Ouyang; Huaguo Liang (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Aging-Temperature-and-Propagation Induced Pulse-Broadening Aware Soft Error Rate Estimation for nano-Scale CMOS. - Aibin Yan; Yafei Ling; Kang Yang; Zhili Chen; Maoxiang Yi (ATS, 2018)

Novel low cost and DNU online self-recoverable RHBD latch design for nanoscale CMOS. - Qian He; Aibin Yan; Chaoping Lai; Yinlei Zhang; Chunming Liu; Zhile Chen; Zhen Wu; Jie Cui 004; Huaguo Liang (ISCAS, 2018)

Radiation Hardening by Design of a Novel Double-Node-Upset-Tolerant Latch Combined with Layout Technique. - Aibin Yan; Zhile Chen; Zhengfeng Huang; Xiangsheng Fang; Maoxiang Yi; Jing Guo 004 (ITC-Asia, 2018)

T2FA: Transparent Two-Factor Authentication. - Jiliang Zhang 002; Xiao Tan; Xiangqi Wang; Aibin Yan; Zheng Qin 001 (IEEE Access, 2018)

Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications. - Aibin Yan; Zhen Wu; Lu Lu; Zhili Chen; Jie Song; Zuobin Ying; Patrick Girard 001; Xiaoqing Wen (ATS, 2019)

Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications. - Aibin Yan; Zhen Wu; Jun Zhou 016; Yuanjie Hu; Yan Chen; Zuobin Ying; Xiaoqing Wen; Patrick Girard 001 (ATS, 2019)

Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications. - Aibin Yan; Yuanjie Hu; Jie Song; Xiaoqing Wen (DATE, 2019)

Design of a Novel Self-Recoverable SRAM Cell Protected Against Soft Errors. - Aibin Yan; Jun Zhou 016; Yuanjie Hu; Yan Chen; Zhen Wu; Tianming Ni (DSA, 2019)

STAHL: A Novel Scan-Test-Aware Hardened Latch Design. - Ruijun Ma; Stefan Holst; Xiaoqing Wen; Aibin Yan; Hui Xu (ETS, 2019)

A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells. - Zhiyuan Song; Aibin Yan; Jie Cui 004; Zhili Chen; Xuejun Li; Xiaoqing Wen; Chaoping Lai; Zhengfeng Huang; Huaguo Liang (ITC-Asia, 2019)

Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory. - Tai Song; Huaguo Liang; Ying Sun; Zhengfeng Huang; Maoxiang Yi; Xiangsheng Fang; Aibin Yan (VTS, 2019)

Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets. - Aibin Yan; Jun Zhou 016; Yuanjie Hu; Jie Cui 004; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (IEEE Access, 2019)

A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application. - Aibin Yan; Kang Yang; Zhengfeng Huang; Jiliang Zhang 002; Jie Cui 004; Xiangsheng Fang; Maoxiang Yi; Xiaoqing Wen (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Novel Double-Node-Upset-Tolerant Memory Cell Designs Through Radiation-Hardening-by-Design and Layout. - Aibin Yan; Zhen Wu; Jing Guo 004; Jie Song; Xiaoqing Wen (IEEE Trans. Reliab., 2019)

A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets. - Aibin Yan; Yan Chen; Jun Zhou 016; Jie Cui 004; Tianming Ni; Xiaoqing Wen; Patrick Girard 001 (ATS, 2020)

HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications. - Aibin Yan; Xiangfeng Feng; Xiaohu Zhao; Hang Zhou; Jie Cui 004; Zuobin Ying; Patrick Girard 001; Xiaoqing Wen (DAC, 2020)

Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications. - Aibin Yan; Zhelong Xu; Jie Cui 004; Zuobin Ying; Zhengfeng Huang; Huaguo Liang; Patrick Girard 001; Xiaoqing Wen (ISCAS, 2020)

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors. - Zhengda Dou; Aibin Yan; Jun Zhou 016; Yuanjie Hu; Yan Chen; Tianming Ni; Jie Cui 004; Patrick Girard 001; Xiaoqing Wen (ITC-Asia, 2020)

Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm. - Tai Song; Huaguo Liang; Tianming Ni; Zhengfeng Huang; Yingchun Lu; Jinlei Wan; Aibin Yan (IEEE Access, 2020)

Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low-Power and Low-Orbit Aerospace Applications. - Aibin Yan; Yan Chen; Zhelong Xu; Zhili Chen; Jie Cui 004; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Aerosp. Electron. Syst., 2020)

Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments. - Aibin Yan; Xiangfeng Feng; Yuanjie Hu; Chaoping Lai; Jie Cui 004; Zhili Chen; Kohei Miyase; Xiaoqing Wen (IEEE Trans. Aerosp. Electron. Syst., 2020)

A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications. - Aibin Yan; Zhelong Xu; Kang Yang; Jie Cui 004; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Aerosp. Electron. Syst., 2020)

Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment. - Aibin Yan; Yuanjie Hu; Jie Cui 004; Zhili Chen; Zhengfeng Huang; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Computers, 2020)

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults. - Tianming Ni; Yao Yao; Hao Chang; Lin Lu; Huaguo Liang; Aibin Yan; Zhengfeng Huang; Xiaoqing Wen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC. - Tianming Ni; Hao Chang; Tai Song; Qi Xu; Zhengfeng Huang; Huaguo Liang; Aibin Yan; Xiaoqing Wen (IEEE Trans. Circuits Syst., 2020)

Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets. - Aibin Yan; Yan Chen; Yuanjie Hu; Jun Zhou 016; Tianming Ni; Jie Cui 004; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Circuits Syst., 2020)

Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs. - Aibin Yan; Yafei Ling; Jie Cui 004; Zhili Chen; Zhengfeng Huang; Jie Song; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Architecture of Cobweb-Based Redundant TSV for Clustered Faults. - Tianming Ni; Dongsheng Liu; Qi Xu; Zhengfeng Huang; Huaguo Liang; Aibin Yan (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A Reliable and Low-Cost Flip-Flop Hardened against Double-Node-Upsets. - Aibin Yan; Aoran Cao; Kuikui Qian; Liang Ding; Zhihui He; Zhengzheng Fan; Xiaoqing Wen (DSA, 2021)

A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments. - Aibin Yan; Aoran Cao; Zhengzheng Fan; Zhelong Xu; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (ACM Great Lakes Symposium on VLSI, 2021)

TPDICE and Sim Based 4-Node-Upset Completely Hardened Latch Design for Highly Robust Computing in Harsh Radiation. - Aibin Yan; Liang Ding; Chuanbo Shan; Haoran Cai; Xiaofeng Chen; Zhanjun Wei; Zhengfeng Huang; Xiaoqing Wen (ISCAS, 2021)

Parallel DICE Cells and Dual-Level CEs based 3-Node-Upset Tolerant Latch Design for Highly Robust Computing. - Aibin Yan; Zijie Zhai; Lele Wang 011; Jixiang Zhang 007; Ningning Cui; Tianming Ni; Xiaoqing Wen (ITC-Asia, 2021)

A Sextuple Cross-Coupled Dual-Interlocked-Storage-Cell based Multiple-Node-Upset Self-Recoverable Latch. - Aibin Yan; Kuikui Qian; Jie Cui 004; Ningning Cui; Tianming Ni; Zhengfeng Huang; Xiaoqing Wen (NANOARCH, 2021)

Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications. - Aibin Yan; Aoran Cao; Zhelong Xu; Jie Cui 004; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (J. Electron. Test., 2021)

Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications. - Aibin Yan; Zhihui He; Jun Zhou 016; Jie Cui 004; Tianming Ni; Zhengfeng Huang; Xiaoqing Wen; Patrick Girard 001 (Microelectron. J., 2021)

A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC. - Tianming Ni; Qi Xu; Zhengfeng Huang; Huaguo Liang; Aibin Yan; Xiaoqing Wen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Intra Coding With Geometric Information for Urban Building Scenes. - Qijun Wang; Aibin Yan; Hua Bao (IEEE Trans. Circuits Syst. Video Technol., 2021)

A Novel TDMA-Based Fault Tolerance Technique for the TSVs in 3D-ICs Using Honeycomb Topology. - Tianming Ni; Zhao Yang; Hao Chang; Xiaoqiang Zhang 001; Lin Lu; Aibin Yan; Zhengfeng Huang; Xiaoqing Wen (IEEE Trans. Emerg. Top. Comput., 2021)

Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS. - Aibin Yan; Chaoping Lai; Yinlei Zhang; Jie Cui 004; Zhengfeng Huang; Jie Song; Jing Guo 004; Xiaoqing Wen (IEEE Trans. Emerg. Top. Comput., 2021)

MRCO: A Multi-ring Convergence Oscillator-based High-Efficiency True Random Number Generator. - Tianming Ni; Qingsong Peng; Jingchang Bian; Liang Yao; Zhengfeng Huang; Aibin Yan; Xiaoqing Wen (AsianHOST, 2022)

A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage. - Aibin Yan; Liang Ding; Zhen Zhou; Zhengfeng Huang; Jie Cui 004; Patrick Girard 001; Xiaoqing Wen (ATS, 2022)

SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments. - Aibin Yan; Zhixing Li; Shiwei Huang; Zijie Zhai; Xiangyu Cheng; Jie Cui 004; Tianming Ni; Xiaoqing Wen; Patrick Girard 001 (DATE, 2022)

Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications. - Aibin Yan; Yu Chen; Shukai Song; Zijie Zhai; Jie Cui 004; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (ACM Great Lakes Symposium on VLSI, 2022)

Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications. - Aibin Yan; Zhihui He; Jing Xiang; Jie Cui 004; Yong Zhou; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (ACM Great Lakes Symposium on VLSI, 2022)

A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology. - Aibin Yan; Zhen Zhou; Shaojie Wei; Jie Cui 004; Yong Zhou; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (ACM Great Lakes Symposium on VLSI, 2022)

Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS. - Aibin Yan; Shukai Song; Jixiang Zhang 007; Jie Cui 004; Zhengfeng Huang; Tianming Ni; Xiaoqing Wen; Patrick Girard 001 (ITC-Asia, 2022)

A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications. - Aibin Yan; Kuikui Qian; Jie Cui 004; Ningning Cui; Zhengfeng Huang; Xiaoqing Wen; Patrick Girard 001 (VTS, 2022)

Broadcast-TDMA: A Cost-Effective Fault-Tolerance Method for TSV Lifetime Reliability Enhancement. - Tianming Ni; Jingchang Bian; Zhao Yang; Mu Nie; Liang Yao; Zhengfeng Huang; Aibin Yan; Xiaoqing Wen (IEEE Des. Test, 2022)

Evaluation and Test of Production Defects in Hardened Latches. - Ruijun Ma; Stefan Holst; Xiaoqing Wen; Aibin Yan; Hui Xu (IEICE Trans. Inf. Syst., 2022)

Machine learning classification algorithm for VLSI test cost reduction. - Tai Song; Zhengfeng Huang; Aibin Yan (Integr., 2022)

A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications. - Aibin Yan; Kuikui Qian; Tai Song; Zhengfeng Huang; Tianming Ni; Yu Chen; Xiaoqing Wen (Integr., 2022)

Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications. - Aibin Yan; Zhengzheng Fan; Liang Ding; Jie Cui 004; Zhengfeng Huang; Qijun Wang; Hao Zheng; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Aerosp. Electron. Syst., 2022)

Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments. - Aibin Yan; Zhelong Xu; Xiangfeng Feng; Jie Cui 004; Zhili Chen; Tianming Ni; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Emerg. Top. Comput., 2022)

A High-Performance and P-Type FeFET-Based Non-Volatile Latch. - Aibin Yan; Yu Chen; Zhengfeng Huang; Jie Cui 004; Xiaoqing Wen (ATS, 2023)

Advanced DICE Based Triple-Node-Upset Recovery Latch with Optimized Overhead for Space Applications. - Aibin Yan; Xuehua Li; Zhongyu Gao; Zhengfeng Huang; Tianming Ni; Xiaoqing Wen (ATS, 2023)

High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology. - Aibin Yan; Zhen Zhou; Liang Ding; Jie Cui 004; Zhengfeng Huang; Xiaoqing Wen; Patrick Girard 001 (DATE, 2023)

A Robust and High-Performance Flip-Flop with Complete Soft-Error Recovery. - Aibin Yan; Xuehua Li; Tianming Ni; Zhengfeng Huang; Xiaoqing Wen (DSA, 2023)

BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell. - Stefan Holst; Ruijun Ma; Xiaoqing Wen; Aibin Yan; Hui Xu (ETS, 2023)

Two Highly Reliable and High-Speed SRAM Cells for Safety-Critical Applications. - Aibin Yan; Yang Chang; Jing Xiang; Hao Luo; Jie Cui 004; Zhengfeng Huang; Tianming Ni; Xiaoqing Wen (ACM Great Lakes Symposium on VLSI, 2023)

A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications. - Aibin Yan; Shaojie Wei; Jinjun Zhang; Jie Cui 004; Jie Song; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (ACM Great Lakes Symposium on VLSI, 2023)

Design of Low-Cost Approximate CMOS Full Adders. - Aibin Yan; Shaojie Wei; Zhixing Li; Jie Cui 004; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (ISCAS, 2023)

Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications. - Aibin Yan; Jing Xiang; Zhengfeng Huang; Tianming Ni; Jie Cui 004; Patrick Girard 001; Xiaoqing Wen (ITC-Asia, 2023)

A Low Overhead and Double-Node-Upset Self-Recoverable Latch. - Aibin Yan; Fan Xia; Tianming Ni; Jie Cui 004; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (ITC-Asia, 2023)

Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness. - Aibin Yan; Chao Zhou; Shaojie Wei; Jie Cui 004; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (ITC-Asia, 2023)

Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications. - Aibin Yan; Aoran Cao; Zhengfeng Huang; Jie Cui 004; Tianming Ni; Patrick Girard 001; Xiaoqing Wen; Jiliang Zhang 002 (IEEE Trans. Emerg. Top. Comput., 2023)

Low Overhead and High Stability Radiation-Hardened Latch for Double/Triple Node Upsets. - Zhengfeng Huang; Hao Wang 169; Dongxing Ma; Huaguo Liang; Yiming Ouyang; Aibin Yan (J. Electron. Test., 2023)

A Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch. - Zhengfeng Huang; Lanxi Duan; Yan Zhang; Tianming Ni; Aibin Yan (IEEE Trans. Aerosp. Electron. Syst., 2023)

Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments. - Aibin Yan; Zhixing Li; Jie Cui 004; Zhengfeng Huang; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Aerosp. Electron. Syst., 2023)

LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments. - Aibin Yan; Zhixing Li; Jie Cui 004; Zhengfeng Huang; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata. - Aibin Yan; Runqi Liu; Jie Cui 004; Tianming Ni; Patrick Girard 001; Xiaoqing Wen; Jiliang Zhang 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications. - Aibin Yan; Yuting He; Xiaoxiao Niu; Jie Cui 004; Tianming Ni; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (IEEE Des. Test, 2023)

Two sextuple cross-coupled SRAM cells with double-node-upset protection and cost optimization for aerospace applications. - Aibin Yan; Jing Xiang; Yang Chang; Zhengfeng Huang; Jie Cui 004; Patrick Girard 001; Xiaoqing Wen (Microelectron. J., 2023)

Overhead Optimized and Quadruple-Node-Upset Self-Recoverable Latch Design Based on Looped C-Element Matrix. - Zhengfeng Huang; Dongxing Ma; Runwu Ji; Huaguo Liang; Aibin Yan; Tai Song; Tianming Ni (IEEE Trans. Aerosp. Electron. Syst., 2023)

Design of True Random Number Generator Based on Multi-Ring Convergence Oscillator Using Short Pulse Enhanced Randomness. - Tianming Ni; Qingsong Peng; Jingchang Bian; Liang Yao; Zhengfeng Huang; Aibin Yan; Senling Wang; Xiaoqing Wen (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

IDLD: Interlocked Dual-Circle Latch Design with Low Cost and Triple-Node-Upset-Recovery for Aerospace Applications. - Aibin Yan; Chen Dong; Xing Guo; Jie Song; Jie Cui 004; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (ACM Great Lakes Symposium on VLSI, 2024)

Nonvolatile and SEU-Recoverable Latch Based on FeFET and CMOS for Energy-Harvesting Devices. - Aibin Yan; Zhuoyuan Lin; Guangzhu Liu; Qingyang Zhang; Zhengfeng Huang; Jie Cui 004; Xiaoqing Wen; Patrick Girard 001 (ISCAS, 2024)

A RO-Integrated-LFSR-Based Nonlinear Strong PUF with Intrinsic Modeling Attacks Resilience. - Jingchang Bian; Zhengfeng Huang; Ruixiang Liu; Yankun Lin; Zhao Yang; Huaguo Liang; Aibin Yan (ITC-Asia, 2024)

SHRCO: Design of an SRAM with High Reliability and Cost Optimization for Safety-Critical Applications. - Yang Chang; Guangzhu Liu; Inam Ullah; Gaoyang Shan; Xiaoqing Wen; Aibin Yan (ITC-Asia, 2024)

SRBML: A Single-Event-Upset Recoverable and BTI-Mitigated Latch Design for Long-Term Reliability Enhancement. - Fan Xia; Jing Zhang; Jehad Ali; Chunjiong Zhang; Xiaoqing Wen; Aibin Yan (ITC-Asia, 2024)

Efficient design approaches to CMOS full adder circuits. - Aibin Yan; Han Bao; Wangjin Jiang; Jie Cui 004; Zhengfeng Huang; Xiaoqing Wen (Microelectron. J., 2024)

A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers. - Qingsong Peng; Jingchang Bian; Zhengfeng Huang; Senling Wang; Aibin Yan (ACM Trans. Design Autom. Electr. Syst., 2024)

Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS. - Aibin Yan; Litao Wang; Jie Cui 004; Zhengfeng Huang; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A Quadruple-Node Upsets Hardened Latch Design Based on Cross-Coupled Elements. - Zhengfeng Huang; Zishuai Li; Liting Sun; Huaguo Liang; Tianming Ni; Aibin Yan (J. Electron. Test., 2024)

Designs of High-Speed Triple-Node-Upset Hardened Latch Based on Dual-Modular-Redundancy. - Zhengfeng Huang; Yan Zhang; Lei Ai; Huaguo Liang; Tianming Ni; Tai Song; Aibin Yan (J. Circuits Syst. Comput., 2024)

FeMPIM: A FeFET-Based Multifunctional Processing-in-Memory Cell. - Aibin Yan; Yu Chen; Zhongyu Gao; Tianming Ni; Zhengfeng Huang; Jie Cui 004; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method. - Aibin Yan; Zhixing Li; Zhongyu Gao; Jing Zhang; Zhengfeng Huang; Tianming Ni; Jie Cui 004; Xiaolei Wang; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

NEST: A Quadruple-Node Upset Recovery Latch Design and Algorithm-Based Recovery Optimization. - Zhengfeng Huang; Liting Sun; Xu Wang; Huaguo Liang; Yingchun Lu; Aibin Yan; Jun Pan; Xiaoqing Wen (IEEE Trans. Aerosp. Electron. Syst., 2024)

Efficient Modulated State Space Model for Mixed-Type Wafer Defect Pattern Recognition. - Mu Nie; Shidong Zhu; Aibin Yan; Cheng Zhuo; Xiaoqing Wen; Tianming Ni (DATE, 2025)

NVSRLO: A FeFET-Based Non-Volatile and SEU-Recoverable Latch Design with Optimized Overhead. - Aibin Yan; Wangjin Jiang; Han Bao; Zhengfeng Huang; Tianming Ni; Xiaoqing Wen; Patrick Girard 001 (DATE, 2025)

TNURML: Triple-Node-Upset-Recovery Magnetic Latch Design with Non-Volatility for Aerospace Applications. - Aibin Yan; Zhiyuan Pei; Xing Guo; Jie Song; Cuiyun Jiang; Huaguo Liang; Xiaoqing Wen; Patrick Girard 001 (ISCAS, 2025)

A lightweight general PUF framework for resisting machine learning attacks. - Tianming Ni; Fei Li; Zhengfeng Huang; Aibin Yan; Senling Wang; Xiaoqing Wen; Mu Nie; Jingchang Bian (Integr., 2025)

A chaotic strong transition effect ring oscillator PUF with effective immunity to modeling attacks. - Jingchang Bian; Xingchen Du; Yingchun Lu; Aibin Yan; Huaguo Liang; Zhengfeng Huang (Microelectron. J., 2025)

Cost Efficient Flip-Flop Designs With Multiple-Node Upset-Tolerance and Algorithm-Based Verifications. - Aibin Yan; Yuting He; Zhengfeng Huang; Wenjie Yan; Jie Cui 004; Xiaolei Wang; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Highly Defect Detectable and SEU-Resilient Robust Scan-Test-Aware Latch Design. - Ruijun Ma; Stefan Holst; Hui Xu; Xiaoqing Wen; Senling Wang; Jiuqi Li; Aibin Yan (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Low-Cost Quadruple-Node-Upset Self-Recoverable Latch Based on Cross-Interlocking. - Zhengfeng Huang; Lei Ai; Xinyu Jiang; Xiaolei Wang; Yingchun Lu; Jun Pan; Tai Song; Xiaoqing Wen; Aibin Yan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Graph-Based Multitask Transfer Learning for Fault Detection and Diagnosis of Few-Shot Analog Circuits. - Zhongyu Gao; Aibin Yan; Zhengfeng Huang; Jie Cui 004; Byeong-Hee Roh; Guangzhu Liu; Patrick Girard 001; Xiaoqing Wen (IEEE Internet Things J., 2025)

Cost-Optimized and Highly Robust Latches Providing Complete Quadruple-Node-Upset Tolerance and Recovery With Algorithm-Based Verifications. - Aibin Yan; Chao Zhou; Tianming Ni; Jing Zhang; Jie Cui 004; Zhengfeng Huang; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Aerosp. Electron. Syst., 2025)

HALTRAV: Design of a High-Performance and Area-Efficient Latch With Triple-Node-Upset Recovery and Algorithm-Based Verifications. - Xing Guo; Jiajia Zhang; Xu Meng; Zhenmin Li; Xiaoqing Wen; Patrick Girard 001; Bin Liang; Aibin Yan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Cost-Optimized Double-Node-Upset-Recovery Latch Designs With Aging Mitigation and Algorithm-Based Verification for Long-Term Robustness Enhancement. - Aibin Yan; Changli Hu; Jing Li; Na Bai; Zhengfeng Huang; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Design of Nonvolatile and Multinode-Upset Recoverable Latches Based on Magnetic Tunnel Junction and CMOS. - Aibin Yan; Yongkang Xu; Yue Zhang; Na Bai; Zhengfeng Huang; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Triple-Node-Upset Recovery High-Impedance-State-Insensitive and Single-Event-Transient Filtering Latch for Aerospace Applications. - Aibin Yan; Zhuoyuan Lin; Yongkang Xu; Na Bai; Jie Cui 004; Zhengfeng Huang; Tianming Ni; Patrick Girard 001; Xiaoqing Wen (IEEE Trans. Aerosp. Electron. Syst., 2025)