Kernel Extraction for Watermarking Combinational Logic Networks. - Aijiao Cui; Chip-Hong Chang (APCCAS, 2006)

Stego-signature at logic synthesis level for digital design IP protection. - Aijiao Cui; Chip-Hong Chang (ISCAS, 2006)

Watermarking for IP Protection through Template Substitution at Logic Synthesis Level. - Aijiao Cui; Chip-Hong Chang (ISCAS, 2007)

Intellectual property authentication by watermarking scan chain in design-for-testability flow. - Aijiao Cui; Chip-Hong Chang (ISCAS, 2008)

IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level. - Aijiao Cui; Chip-Hong Chang; Sofiène Tahar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

An Improved Publicly Detectable Watermarking Scheme based on Scan Chain Ordering. - Aijiao Cui; Chip-Hong Chang (ISCAS, 2009)

Synthesis-for-Testability Watermarking for Field Authentication of VLSI Intellectual Property. - Chip-Hong Chang; Aijiao Cui (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A hybrid watermarking scheme for sequential functions. - Aijiao Cui; Chip-Hong Chang; Li Zhang (ISCAS, 2011)

A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit Design. - Aijiao Cui; Chip-Hong Chang; Sofiène Tahar; Amr Talaat Abdel-Hamid (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

A post-processing scan-chain watermarking scheme for VLSI intellectual property protection. - Aijiao Cui; Chip-Hong Chang (APCCAS, 2012)

An Efficient Zero-Aliasing Space Compactor Based on Elementary Gates Combined with XOR Gates. - Yongxia Liu; Aijiao Cui (CAD/Graphics, 2013)

A power-efficient scan tree design by exploring the Q'-D connection. - Linfeng Chen; Aijiao Cui (ISCAS, 2013)

A low-overhead dynamic watermarking scheme on scan design for easy authentication. - Aijiao Cui; Wei Liang; Gang Qu 001 (ISCAS, 2014)

An improved scan cell ordering method using the scan cells with complementary outputs. - Mengyang Li; Aijiao Cui; Tingting Yu (ISIC, 2014)

A refined affine approximation method of multiplication for range analysis in word-length optimization. - Ruiyi Sun; Yan Zhang; Aijiao Cui (EURASIP J. Adv. Signal Process., 2014)

Reliable and Anti-cloning PUFs Based on Configurable Ring Oscillators. - Mingze Gao; Khai Lai; Jiliang Zhang 002; Gang Qu 001; Aijiao Cui; Qiang Zhou 001 (CAD/Graphics, 2015)

An improved scan design for minimization of test power under routing constraint. - Aijiao Cui; Tingting Yu; Gang Qu 001; Mengyang Li (ISCAS, 2015)

A new decompressor with ordered parallel scan design for reduction of test data and test time. - Tingting Yu; Aijiao Cui; Mengyang Li; André Ivanov (ISCAS, 2015)

Design of Optimal Scan Tree Based on Compact Test Patterns for Test Time Reduction. - Linfeng Chen; Aijiao Cui; Chip-Hong Chang (IEEE Trans. Computers, 2015)

Ultra-Low Overhead Dynamic Watermarking on Scan Design for Hard IP Protection. - Aijiao Cui; Gang Qu 001; Yan Zhang (IEEE Trans. Inf. Forensics Secur., 2015)

Digital Fingerprint: A Practical Hardware Security Primitive. - Gang Qu 001; Carson Dunbar; Xi Chen; Aijiao Cui (Digital Fingerprinting, 2016)

An ultra-low overhead LUT-based PUF for FPGA. - Jiadong Wang; Aijiao Cui; Mengyang Li; Gang Qu 001; Huawei Li 001 (AsianHOST, 2016)

An improved test power optimization method by insertion of linear functions. - Lucheng He; Aijiao Cui; Mengyang Li; André Ivanov (ISCAS, 2016)

A new countermeasure against scan-based side-channel attacks. - Yanhui Luo; Aijiao Cui; Gang Qu 001; Huawei Li 001 (ISCAS, 2016)

A New Active IC Metering Technique Based on Locking Scan Cells. - Aijiao Cui; Xuesen Qian; Gang Qu 001; Huawei Li 001 (ATS, 2017)

How to Secure Scan Design Against Scan-Based Side-Channel Attacks? - Wei Zhou; Aijiao Cui; Huawei Li 001; Gang Qu 001 (ATS, 2017)

Practical IP watermarking and fingerprinting methods for ASIC designs. - Xi Chen; Gang Qu 001; Aijiao Cui (ISCAS, 2017)

A new watermarking scheme on scan chain ordering for hard IP protection. - Xiaonan Huang; Aijiao Cui; Chip-Hong Chang (ISCAS, 2017)

Scan chain based IP fingerprint and identification. - Xi Chen; Gang Qu 001; Aijiao Cui; Carson Dunbar (ISQED, 2017)

Why current secure scan designs fail and how to fix them? - Aijiao Cui; Yanhui Luo; Huawei Li 001; Gang Qu 001 (Integr., 2017)

Static and Dynamic Obfuscations of Scan Data Against Scan-Based Side-Channel Attacks. - Aijiao Cui; Yanhui Luo; Chip-Hong Chang (IEEE Trans. Inf. Forensics Secur., 2017)

A low-overhead PUF based on parallel scan design. - Wenxuan Wang; Aijiao Cui; Gang Qu 001; Huawei Li 001 (ASP-DAC, 2018)

A New Scheme to Extract PUF Information by Scan Chain. - Aijiao Cui; Wei Zhou; Gang Qu 001; Huawei Li 001 (ATS, 2018)

Balancing Testability and Security by Configurable Partial Scan Design. - Xi Chen; Omid Aramoon; Gang Qu 001; Aijiao Cui (ITC-Asia, 2018)

Partial Scan Design Against Scan-Based Side Channel Attacks. - Xi Chen; Zhaojun Lu; Gang Qu 001; Aijiao Cui (TrustCom/BigDataSE, 2018)

Identification of State Registers of FSM Through Full Scan by Data Analytics. - Chengkang He; Aijiao Cui; Chip-Hong Chang (AsianHOST, 2019)

A New Pay-Per-Use Scheme for the Protection of FPGA IP. - Peiqi Sun; Aijiao Cui (ISCAS, 2019)

A Memristor-based Scan Hold Flip-Flop. - Aijiao Cui; Zhenxing Chang; Ziming Wang; Gang Qu 001; Huawei Li 001 (NVMSA, 2019)

A Secure and Low-overhead Active IC Metering Scheme. - Aijiao Cui; Yan Yang; Gang Qu 001; Huawei Li 001 (VTS, 2019)

A New Aging Sensor for the Detection of Recycled ICs. - Zhichao Xu; Aijiao Cui; Gang Qu 001 (ACM Great Lakes Symposium on VLSI, 2020)

How to Retrieve PUF Response from a Fabricated Chip Securely? - Aijiao Cui; Yuxi Wang (ISQED, 2020)

A Low-Cost Fault Injection Attack Resilient FSM Design. - Ziming Wang; Aijiao Cui; Gang Qu 001 (SoCC, 2020)

A New Secure Scan Design with PUF-based Key for Authentication. - Qidong Wang; Aijiao Cui; Gang Qu 001; Huawei Li 001 (VTS, 2020)

A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash. - Aijiao Cui; Mengyang Li; Gang Qu 001; Huawei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Novel Memristor-based Nonvolatile D Latch and Flip-flop Designs. - Zhenxing Chang; Aijiao Cui; Ziming Wang; Gang Qu 001 (ISQED, 2021)

Identification of Counter Registers through Full Scan Chain. - Qidong Wang; Aijiao Cui; Gang Qu 001 (ITC-Asia, 2021)

A New PUF Based Lock and Key Solution for Secure In-Field Testing of Cryptographic Chips. - Aijiao Cui; Chip-Hong Chang; Wei Zhou; Yue Zheng (IEEE Trans. Emerg. Top. Comput., 2021)

Identification of FSM State Registers by Analytics of Scan-Dump Data. - Aijiao Cui; Chengkang He; Chip-Hong Chang; Hao Lu (IEEE Trans. Inf. Forensics Secur., 2021)

A Memristor-based Secure Scan Design against the Scan-based Side-Channel Attacks. - Mengqiang Lu; Aijiao Cui; Yan Shao; Gang Qu 001 (ACM Great Lakes Symposium on VLSI, 2022)

Building Hardware Security Primitives Using Scan-based Design-for-Testability. - Omid Aramoon; Gang Qu 001; Aijiao Cui (MWSCAS, 2022)

SATAM: A SAT Attack Resistant Active Metering Against IC Overbuilding. - Aijiao Cui; Zhen Weng; Hui Zhang; Gang Qu 001; Huawei Li 001 (IEEE Trans. Emerg. Top. Comput., 2022)

A Lightweight Authentication Scheme with PE-Based Unclonable Label. - Renchao Li; Zhen Weng; Aijiao Cui; Gang Qu 001 (AsianHOST, 2023)

A Low-overhead PUF-based Secure Scan Design. - Wei Zhou; Aijiao Cui; Cassi Chen; Gang Qu 001 (ISQED, 2023)

SecRiSBen: A RISC-V based SoC Benchmark for Evaluation of Security Verification Tools. - Maoyuan Cai; Aijiao Cui; Yier Jin (AsianHOST, 2024)

A Hardware Security Evaluation Platform on RISC-V SoC. - Xiaolong Cheng; Aijiao Cui; Yier Jin (ITC-Asia, 2024)

Non-Invasive Reverse Engineering of One-Hot Finite State Machines Using Scan Dump Data. - Zhaoxuan Dong; Aijiao Cui; Hao Lu (IEEE Trans. Emerg. Top. Comput., 2024)

Acceleration of the Bootstrapping in TFHE by FPGA. - Jian Zhang; Aijiao Cui; Yier Jin (IEEE Trans. Emerg. Top. Comput., 2025)