Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. - Naran Sirisantana; Aiqun Cao; Shawn Davidson; Cheng-Kok Koh; Kaushik Roy 001 (ISLPED, 2001)

Synthesis of Selectively Clocked Skewed Logic Circuits. - Aiqun Cao; Naran Sirisantana; Cheng-Kok Koh; Kaushik Roy 001 (ISQED, 2002)

Integer linear programming-based synthesis of skewed logic circuits. - Aiqun Cao; Naran Sirisantana; Cheng-Kok Koh; Kaushik Roy 001 (ASP-DAC, 2003)

Non-Crossing OBDDs for Mapping to Regular Circuit Structures. - Aiqun Cao; Cheng-Kok Koh (ICCD, 2003)

Post-layout logic optimization of domino circuits. - Aiqun Cao; Cheng-Kok Koh (DAC, 2004)

Post-layout logic duplication for synthesis of domino circuits with complex gates. - Aiqun Cao; Ruibing Lu; Cheng-Kok Koh (ASP-DAC, 2005)

Improving the scalability of SAMBA bus architecture. - Ruibing Lu; Aiqun Cao; Cheng-Kok Koh (ASP-DAC, 2005)

Synthesis of skewed logic circuits. - Aiqun Cao; Naran Sirisantana; Cheng-Kok Koh; Kaushik Roy 001 (ACM Trans. Design Autom. Electr. Syst., 2005)

Postlayout optimization for synthesis of Domino circuits. - Aiqun Cao; Ruibing Lu; Chen Li 004; Cheng-Kok Koh (ACM Trans. Design Autom. Electr. Syst., 2006)

SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. - Ruibing Lu; Aiqun Cao; Cheng-Kok Koh (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Clock mesh framework. - Pinaki Chakrabarti; Vikram Bhatt; Dwight D. Hill; Aiqun Cao (ISQED, 2012)

Triple-play of Hyperconvergency, Analytics, and AI Innovations in the SysMoore Era. - Aiqun Cao (ISPD, 2022)