Transistor-level based defect tolerance for reliable nanoelectronics. - Aiman H. El-Maleh; Bashir M. Al-Hashimi; Aissa Melouki (AICCSA, 2008)

Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism. - Saket Srivastava; Aissa Melouki; Bashir M. Al-Hashimi (NANOARCH, 2009)

Defect-tolerant n2-transistor structure for reliable nanoelectronic designs. - Aiman H. El-Maleh; Bashir M. Al-Hashimi; Aissa Melouki; Farhan Khan (IET Comput. Digit. Tech., 2009)

Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. - Aissa Melouki; Saket Srivastava; Bashir M. Al-Hashimi (IET Comput. Digit. Tech., 2010)