Hardware Architecture for Optical Flow Estimation in Real Time. - Aitzol Zuloaga; José Luis Martín 001; Joseba Ezquerra (ICIP (3), 1998)

Software Workbench for Movement Estimation based on Optical Flow Computation. - José Luis Martín 001; Aitzol Zuloaga; Josu Cruzado (VIIP, 2001)

Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements. - Unai Bidarte; Armando Astarloa; Aitzol Zuloaga; Jaime Jimenez; Iñigo Martínez de Alegría (FPL, 2003)

A Self-Reconfiguration Framework for Multiprocessor CSoPCs. - Armando Astarloa; Jesús Lázaro 001; Unai Bidarte; José Luis Martín 001; Aitzol Zuloaga (FPL, 2004)

Doppler Location Algorithm for Wireless Sensor Networks. - Jagoba Arias; Jesús Lázaro 001; Aitzol Zuloaga; Jaime Jimenez (International Conference on Wireless Networks, 2004)

Co-simulation Virtual Platform for Reconfigurable Multiprocessor Hybrid Cores Development. - Armando Astarloa; Jesús Lázaro 001; Jagoba Arias; Unai Bidarte; Aitzol Zuloaga (MSV/AMCS, 2004)

Malguki: an RSSI based ad hoc location algorithm. - Jagoba Arias; Aitzol Zuloaga; Jesús Lázaro 001; Jon Andreu; Armando Astarloa (Microprocess. Microsystems, 2004)

Hardware implementation of optical flow constraint equation using FPGAs. - José L. Martín-Sánchez; Aitzol Zuloaga; Carlos Cuadrado; Jesús Lázaro 001; Unai Bidarte (Comput. Vis. Image Underst., 2005)

Multiprocessor SoPC-Core for FAT volume computation. - Armando Astarloa; Unai Bidarte; Jesús Lázaro 001; Aitzol Zuloaga; Jagoba Arias (Microprocess. Microsystems, 2005)

Node Synchronization in Wireless Sensor Networks. - Jagoba Arias; Eduardo Santos; Itziar Marín; Jaime Jimenez; Jesús Lázaro 001; Aitzol Zuloaga (ICWMC, 2006)

SOM Segmentation of gray scale images for optical recognition. - Jesús Lázaro 001; Jagoba Arias; José Luis Martín 001; Aitzol Zuloaga; Carlos Cuadrado (Pattern Recognit. Lett., 2006)

Comparison of two designs for the multifunction vehicle bus. - Jaime Jimenez; José Luis Martín 001; Aitzol Zuloaga; Unai Bidarte; Jagoba Arias (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

GPS-less location algorithm for wireless sensor networks. - Jagoba Arias; Jesús Lázaro 001; Aitzol Zuloaga; Jaime Jimenez; Armando Astarloa (Comput. Commun., 2007)

Hardware architecture for a general regression neural network coprocessor. - Jesús Lázaro 001; Jagoba Arias; Armando Astarloa; Unai Bidarte; Aitzol Zuloaga (Neurocomputing, 2007)

Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs. - Armando Astarloa; Aitzol Zuloaga; Unai Bidarte; José Luis Martín 001; Jesús Lázaro 001; Jaime Jimenez (J. Syst. Archit., 2007)

Design of a Master Device for the Multifunction Vehicle Bus. - Jaime Jimenez; José Luis Martín 001; Unai Bidarte; Armando Astarloa; Aitzol Zuloaga (IEEE Trans. Veh. Technol., 2007)

A Novel Technique for Low Latency Data Gathering in Wireless Sensor Networks. - Itziar Marín; Aitzol Zuloaga; Iker Losada (DSD, 2008)

LL-MAC: A low latency MAC protocol for wireless self-organised networks. - Itziar Marín; Jagoba Arias; E. Arceredillo; Aitzol Zuloaga; Iker Losada; Jon Mabe (Microprocess. Microsystems, 2008)

AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications. - Jesús Lázaro 001; Armando Astarloa; Unai Bidarte; Jaime Jimenez; Aitzol Zuloaga (ARC, 2009)

DNAX-BCU: An Un-clonable Cost-conscious SoPC Implementation for Bus Coupling Units of the European Installation Bus. - Armando Astarloa; Jesús Lázaro 001; Unai Bidarte; Aitzol Zuloaga; Jaime Jimenez (ICDCS Workshops, 2009)

PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable Systems. - Armando Astarloa; Jesús Lázaro 001; Unai Bidarte; Aitzol Zuloaga; Jaime Jimenez (ReConFig, 2009)

An Autonomous Fault Tolerant System for CAN Communications. - Armando Astarloa; Jesús Lázaro 001; Unai Bidarte; Aitzol Zuloaga; José Luis Martín 001 (IEA/AIE (3), 2010)

An automatic experimental set-up for robustness analysis of designs implemented on SRAM FPGAS. - Uli Kretzschmar; Armando Astarloa; Jesús Lázaro 001; Jaime Jimenez; Aitzol Zuloaga (SoC, 2011)

NoCmodel: An extensible framework for Network-on-Chips modeling. - Oscar Daniel Diaz; Armando Astarloa; Aitzol Zuloaga; Jesús Lázaro 001; Jaime Jimenez (ReCoSoC, 2011)

I2CSec: A secure serial Chip-to-Chip communication protocol. - Jesús Lázaro 001; Armando Astarloa; Aitzol Zuloaga; Unai Bidarte; Jaime Jimenez (J. Syst. Archit., 2011)

High availability automation networks: PRP and HSR ring implementations. - Jose Angel Araujo; Jesús Lázaro 001; Armando Astarloa; Aitzol Zuloaga; Alain García (ISIE, 2012)

PRP and HSR version 1 (IEC 62439-3 Ed.2), improvements and a prototype implementation. - José Ángel Araujo; Jesús Lázaro 001; Armando Astarloa; Aitzol Zuloaga; Alain García (IECON, 2013)

Duplicate and circulating frames discard methods for PRP and HSR (IEC62439-3). - José Ángel Araujo; Jesús Lázaro 001; Armando Astarloa; Aitzol Zuloaga; Naiara Moreira (IECON, 2013)

System-on-Chip implementation of Reliable Ethernet Networks nodes. - Armando Astarloa; Jesús Lázaro 001; Unai Bidarte; Aitzol Zuloaga; Mikel Idirin (IECON, 2013)

Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor. - Julen Gomez-Cornejo; Aitzol Zuloaga; Uli Kretzschmar; Unai Bidarte; Jaime Jimenez (IECON, 2013)

Cost-effective redundancy for ethernet train communications using HSR. - Aitzol Zuloaga; Armando Astarloa; Jaime Jimenez; Jesús Lázaro 001; Jose Angel Araujo (ISIE, 2014)

PRP and HSR for High Availability Networks in Power Utility Automation: A Method for Redundant Frames Discarding. - José Ángel Araujo; Jesús Lázaro 001; Armando Astarloa; Aitzol Zuloaga; Jose Ignacio Garate (IEEE Trans. Smart Grid, 2015)

Intelligent gateway for Industry 4.0-compliant production. - Armando Astarloa; Unai Bidarte; Jaime Jimenez; Aitzol Zuloaga; Jesús Lázaro 001 (IECON, 2016)

A novel BRAM content accessing and processing method based on FPGA configuration bitstream. - Julen Gomez-Cornejo; Aitzol Zuloaga; Igor Villalta; Javier Del Ser; Uli Kretzschmar; Jesús Lázaro 001 (Microprocess. Microsystems, 2017)

Data content scrubbing approach for SRAM based FPGA designs. - Julen Gomez-Cornejo; Igor Villalta; Itxaso Aranzabal; Iraide Lopez; Aitzol Zuloaga (ISIE, 2022)

AXI Lite Redundant On-Chip Bus Interconnect for High Reliability Systems. - Jesús Lázaro 001; Armando Astarloa; Aitzol Zuloaga; José Ángel Araujo; Jaime Jiménez (IEEE Trans. Reliab., 2024)