Mismatch Characterization of Ring Oscillators. - Ajay Balankutty; T. C. Chih; C. Y. Chen; Peter R. Kinget (CICC, 2007)

A 0.6V 32.5mW Highly Integrated Receiver for 2.4GHz ISM-Band Applications. - Ajay Balankutty; Shih-An Yu; Yiping Feng; Peter R. Kinget (ISSCC, 2008)

A 2.4-GHz ISM-Band Sliding-IF Receiver With a 0.5-V Supply. - Nebojsa Stanic; Ajay Balankutty; Peter R. Kinget; Yannis P. Tsividis (IEEE J. Solid State Circuits, 2008)

A 0.6-V Zero-IF/Low-IF Receiver With Integrated Fractional-N Synthesizer for 2.4-GHz ISM-Band Applications. - Ajay Balankutty; Shih-An Yu; Yiping Feng; Peter R. Kinget (IEEE J. Solid State Circuits, 2010)

A 12-element 60GHz CMOS phased array transmitter on LTCC package with integrated antennas. - Ajay Balankutty; Stefano Pellerano; Telesphor Kamgaing; Kranti Tantwai; Yorgos Palaskas (A-SSCC, 2011)

An Ultra-Low Voltage, Low-Noise, High Linearity 900-MHz Receiver With Digitally Calibrated In-Band Feed-Forward Interferer Cancellation in 65-nm CMOS. - Ajay Balankutty; Peter R. Kinget (IEEE J. Solid State Circuits, 2011)

32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver. - Hasnain Lakdawala; Mark Schaecher; Chang-Tsung Fu; Rahul Dilip Limaye; Jon Duster; Yulin Tan; Ajay Balankutty; Erkan Alpman; Chun C. Lee; Satoshi Suzuki; Brent R. Carlton; Hyung Seok Kim; et al. (ISSCC, 2012)

A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS. - Yulin Tan; Jon Duster; Chang-Tsung Fu; Erkan Alpman; Ajay Balankutty; Chun C. Lee; Ashoke Ravi; Stefano Pellerano; Kailash Chandrashekar; Hyung Seok Kim; Brent R. Carlton; Satoshi Suzuki; et al. (VLSIC, 2012)

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver. - Hasnain Lakdawala; Mark Schaecher; Chang-Tsung Fu; Rahul Dilip Limaye; Jon Duster; Yulin Tan; Ajay Balankutty; Erkan Alpman; Chun C. Lee; Khoa Minh Nguyen; Hyung-Jin Lee; Ashoke Ravi; et al. (IEEE J. Solid State Circuits, 2013)

A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS. - Amr Elshazly; Ajay Balankutty; Yan-Yu Huang; Kai Yu 016; Frank O'Mahony (VLSIC, 2014)

3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS. - Jihwan Kim; Ajay Balankutty; Amr Elshazly; Yan-Yu Huang; Hang Song; Kai Yu 016; Frank O'Mahony (ISSCC, 2015)

A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS. - Jihwan Kim; Ajay Balankutty; Rajeev K. Dokania; Amr Elshazly; Hyung Seok Kim; Sandipan Kundu; Skyler Weaver; Kai Yu 016; Frank O'Mahony (ISSCC, 2018)

56G/112G Link Foundations Standards, Link Budgets & Models. - Ganesh Balamurugan; Ajay Balankutty; Chun-Ming Hsu (CICC, 2019)

A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET. - Jihwan Kim; Ajay Balankutty; Rajeev K. Dokania; Amr Elshazly; Hyung Seok Kim; Sandipan Kundu; Dan Shi; Skyler Weaver; Kai Yu 016; Frank O'Mahony (IEEE J. Solid State Circuits, 2019)

8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm2, 1mm Package-on-Package. - Wilfred Gomes; Sanjeev Khushu; Doug B. Ingerly; Patrick N. Stover; Nasirul I. Chowdhury; Frank O'Mahony; Ajay Balankutty; Noam Dolev; Martin G. Dixon; Lei Jiang; Surya Prekke; Biswajit Patra; et al. (ISSCC, 2020)

8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS. - Jihwan Kim; Sandipan Kundu; Ajay Balankutty; Matthew Beach; Bong Chan Kim; Stephen Kim; Yutao Liu; Savyassachi Keshava Murthy; Priya Wali; Kai Yu 016; Hyung Seok Kim; Chuanchang Liu; et al. (ISSCC, 2021)

A 56GHz Receiver Analog Front End for 224Gb/s PAM-4 SerDes in 10nm CMOS. - Shiva Kiran; Ajay Balankutty; Yutao Liu; Rajeev Dokania; Hariprasath Venkataraman; Priya Wali; Stephen Kim; Yoel Krupnik; Ariel Cohen 001; Frank O'Mahony (VLSI Circuits, 2021)

A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation. - Yoav Segal; Amir Laufer; Ahmad Khairi; Yoel Krupnik; Marco Cusmai; Itamar Levin; Ari Gordon; Yaniv Saban; Vitali Rahinskj; Gadi Ori; Noam Familia; Stas Litski; et al. (ISSCC, 2022)

A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET. - Jihwan Kim; Sandipan Kundu; Ajay Balankutty; Matthew Beach; Bong Chan Kim; Stephen T. Kim; Yutao Liu; Savyasaachi Keshava Murthy; Priya Wali; Kai Yu 016; Hyung Seok Kim; Chuanchang Liu; et al. (IEEE J. Solid State Circuits, 2022)

A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels. - Ahmad Khairi; Yoel Krupnik; Amir Laufer; Yoav Segal; Marco Cusmai; Itamar Levin; Ari Gordon; Yaniv Sabag; Vitali Rahinski; Idan Lotan; Gadi Ori; Noam Familia; et al. (IEEE J. Solid State Circuits, 2023)

Design of 224Gb/s DSP-Based Transceiver in CMOS Technology: Signal Integrity, Architecture, Circuits, and Packaging. - Jihwan Kim; Ariel Cohen 001; Mike Peng Li; Ajay Balankutty; Sandipan Kundu; Ahmad Khairi; Yoel Krupnik; Yoav Segal; Marco Cusmai; Dror Lazar; Ari Gordon; Noam Familia; et al. (CICC, 2024)