Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPs/SoCs - Abhishek Jain 003; Giuseppe Bonanno; Hima Gupta; Ajay Goyal (CoRR, 2013)

Metasynthesis for Designing Automotive SoCs. - Wolfgang Ecker; Michael Velten; Leily Zafari; Ajay Goyal (DAC, 2014)

The metamodeling approach to system level synthesis. - Wolfgang Ecker; Michael Velten; Leily Zafari; Ajay Goyal (DATE, 2014)

The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems. - Oliver Bringmann 001; Wolfgang Ecker; Andreas Gerstlauer; Ajay Goyal; Daniel Mueller-Gritschneder; Prasanth Sasidharan; Simranjit Singh (DATE, 2015)