Leakage Power Reduction Technique by using FinFET Technology. - Ajay Kumar Dadoria; Kavita Khare; R. P. Singh (ICTCS, 2016)

Low-Power High Speed 1-bit Full Adder Circuit Design. - Shailesh Dwivedi; Kavita Khare; Ajay Kumar Dadoria (ICTCS, 2016)

New Leakage Reduction Techniques for FinFET Technology with Its Application. - Ajay Kumar Dadoria; Kavita Khare; Tarun Kumar Gupta; R. P. Singh (J. Circuits Syst. Comput., 2018)

Design and Analysis of Low-Power Adiabatic Logic Circuits by Using CNTFET Technology. - Ajay Kumar Dadoria; Kavita Khare (Circuits Syst. Signal Process., 2019)