Arithmetic Transformations to Maximise the Use of Compressor Trees. - Paolo Ienne; Ajay Kumar Verma (DELTA, 2004)

Improved use of the carry-save representation for the synthesis of complex arithmetic circuits. - Ajay Kumar Verma; Paolo Ienne (ICCAD, 2004)

Towards the automatic exploration of arithmetic-circuit architectures. - Ajay Kumar Verma; Paolo Ienne (DAC, 2006)

Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography. - Johann Großschädl; Paolo Ienne; Laura Pozzi 001; Stefan Tillich; Ajay Kumar Verma (DATE, 2006)

Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. - Ajay Kumar Verma; Paolo Ienne (ASP-DAC, 2007)

An optimistic and conservative register assignment heuristic for chordal graphs. - Philip Brisk; Ajay Kumar Verma; Paolo Ienne (CASES, 2007)

Rethinking custom ISE identification: a new processor-agnostic method. - Ajay Kumar Verma; Philip Brisk; Paolo Ienne (CASES, 2007)

Enhancing FPGA Performance for Arithmetic Circuits. - Philip Brisk; Ajay Kumar Verma; Paolo Ienne; Hadi Parandeh-Afshar (DAC, 2007)

Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. - Ajay Kumar Verma; Philip Brisk; Paolo Ienne (DAC, 2007)

Automatic synthesis of compressor trees: reevaluating large counters. - Ajay Kumar Verma; Paolo Ienne (DATE, 2007)

Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. - Philip Brisk; Ajay Kumar Verma; Paolo Ienne (ICCAD, 2007)

Fast, quasi-optimal, and pipelined instruction-set extensions. - Ajay Kumar Verma; Philip Brisk; Paolo Ienne (ASP-DAC, 2008)

Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. - Ajay Kumar Verma; Philip Brisk; Paolo Ienne (DATE, 2008)

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Ajay Kumar Verma; Philip Brisk; Frank K. Gürkaynak; Yusuf Leblebici; Paolo Ienne (FPGA, 2008)

Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits. - Ajay Kumar Verma; Philip Brisk; Paolo Ienne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Challenges in Automatic Optimization of Arithmetic Circuits. - Ajay Kumar Verma; Philip Brisk; Paolo Ienne (IEEE Symposium on Computer Arithmetic, 2009)

Hybrid LZA: a near optimal implementation of the leading zero anticipator. - Amit Verma 002; Ajay Kumar Verma; Philip Brisk; Paolo Ienne (ASP-DAC, 2009)

Iterative layering: Optimizing arithmetic circuits by structuring the information flow. - Ajay Kumar Verma; Philip Brisk; Paolo Ienne (ICCAD, 2009)

Arithmetic optimization for custom instruction set synthesis. - Ajay Kumar Verma; Yi Zhu; Philip Brisk; Paolo Ienne (SASP, 2009)

Optimistic chordal coloring: a coalescing heuristic for SSA form programs. - Philip Brisk; Ajay Kumar Verma; Paolo Ienne (Des. Autom. Embed. Syst., 2009)

Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Ajay Kumar Verma; Seyed-Hosein Attarzadeh-Niaki; Chrysostomos Nicopoulos; Frank K. Gürkaynak; Philip Brisk; Yusuf Leblebici; Paolo Ienne (ACM Trans. Reconfigurable Technol. Syst., 2009)

Generating Distributed Query Processing Plans Using Genetic Algorithm. - T. V. Vijay Kumar; Vikram Singh 005; Ajay Kumar Verma (DSDE, 2010)

Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. - Amit Verma 002; Ajay Kumar Verma; Hadi Parandeh-Afshar; Philip Brisk; Paolo Ienne (FPL, 2010)

An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form. - Philip Brisk; Ajay Kumar Verma; Paolo Ienne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration. - Ajay Kumar Verma; Philip Brisk; Paolo Ienne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Improving FPGA Performance for Carry-Save Arithmetic. - Hadi Parandeh-Afshar; Ajay Kumar Verma; Philip Brisk; Paolo Ienne (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Pre-Synthesis Optimization of Arithmetic Circuits. - Ajay Kumar Verma (2010)

Document image binarization using wavelets for OCR applications. - C. Patvardhan 001; Ajay Kumar Verma; C. Vasantha Lakshmi (ICVGIP, 2012)

Deep learning based network similarity for model selection. - Kushal Veer Singh; Ajay Kumar Verma; Lovekesh Vig (Data Sci., 2021)