Pragmatic design of gated-diode FinFET DRAMs. - Ajay N. Bhoj; Niraj K. Jha (ICCD, 2009)

Die-level leakage power analysis of FinFET circuits considering process variations. - Prateek Mishra; Ajay N. Bhoj; Niraj K. Jha (ISQED, 2010)

Fault modeling for FinFET circuits. - Muzaffer O. Simsir; Ajay N. Bhoj; Niraj K. Jha (NANOARCH, 2010)

Gated-diode FinFET DRAMs: Device and circuit design-considerations. - Ajay N. Bhoj; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2010)

Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology. - Ajay N. Bhoj; Niraj K. Jha (ISQED, 2011)

Efficient Methodologies for 3-D TCAD Modeling of Emerging Devices and Circuits. - Ajay N. Bhoj; Rajiv V. Joshi; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology. - Ajay N. Bhoj; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2013)

3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits. - Ajay N. Bhoj; Rajiv V. Joshi; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs. - Ajay N. Bhoj; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Design of Efficient Content Addressable Memories in High-Performance FinFET Technology. - Debajit Bhattacharya; Ajay N. Bhoj; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction. - Rajiv V. Joshi; Keunwoo Kim; Rouwaida Kanj; Ajay N. Bhoj; Matthew M. Ziegler; Phil Oldiges; Pranita Kerber; Robert Wong; Terence Hook; Sudesh Saroop; Carl Radens; Chun-Chen Yeh (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism. - Sourindra Chaudhuri; Ajay N. Bhoj; Debajit Bhattacharya; Niraj K. Jha (VLSID, 2016)