Low-power short-channel single-ended current-steered CMOS logic-gate for mixed-signal systems. - Ajay Taparia; Thayamkulangara R. Viswanathan (ISCAS, 2008)

Power-Supply Noise Reduction Using Active Inductors in Mixed-Signal Systems. - Ajay Taparia; Bhaskar Banerjee; Thayamkulangara R. Viswanathan (IEEE Trans. Very Large Scale Integr. Syst., 2011)

CS-CMOS: A Low-Noise Logic Family for Mixed Signal SoCs. - Ajay Taparia; Bhaskar Banerjee; Thayamkulangara R. Viswanathan (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A 12 bit, 2-MS/s, 0.016-mm2 column-parallel readout cyclic ADC, having 50% reduced slew rate requirement due to feed-forward spike eliminator. - Saikrishna Ganta; Alfredo Tomasini; Ajay Taparia; Taehee Cho; Mandar Kulkarni; Ozan Erdogan (ESSCIRC, 2016)