Re-targeting Optimization Sequences from Scalar Processors to FPGAs in HLS compilers (Abstract Only). - Ronak Kogta; Suresh Purini; Ajit Mathew (FPGA, 2016)

MV-RLU: Scaling Read-Log-Update with Multi-Versioning. - Jaeho Kim; Ajit Mathew; Sanidhya Kashyap; Madhava Krishnan Ramanathan; Changwoo Min (ASPLOS, 2019)

Durable Transactional Memory Can Scale with Timestone. - Madhava Krishnan Ramanathan; Jaeho Kim; Ajit Mathew; Xinwei Fu; Anthony Demeri; Changwoo Min; Sudarsun Kannan (ASPLOS, 2020)

HydraList: A Scalable In-Memory Index Using Asynchronous Updates and Partial Replication. - Ajit Mathew; Changwoo Min (Proc. VLDB Endow., 2020)

TIPS: Making Volatile Index Structures Persistent with DRAM-NVMM Tiering. - Madhava Krishnan Ramanathan; Wook-Hee Kim; Xinwei Fu; Sumit Kumar Monga; Hee Won Lee; Minsung Jang; Ajit Mathew; Changwoo Min (USENIX ATC, 2021)