An Algorithm for Optimal Logic Design Using Multiplexers. - Ajit Pal (IEEE Trans. Computers, 1986)

An Efficient Graph-Theoretic Algorithm for Three-Layer Channel Routing. - Rajat Kumar Pal; Ajit Pal (VLSI Design, 1992)

NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient Heuristic. - Rajat Kumar Pal; Sudebkumar Prasant Pal; Ajit Pal; Alak K. Dutta (VLSI Design, 1993)

A general graph theoretic framework for multi-layer channel routing. - Rajat Kumar Pal; A. K. Datta; Sudebkumar Prasant Pal; M. M. Das; Ajit Pal (VLSI Design, 1995)

Computing area and wire length efficient routes for channels. - Rajat Kumar Pal; Sudebkumar Prasant Pal; M. M. Das; Ajit Pal (VLSI Design, 1995)

A layered architecture for real-time systems. - N. V. Satyanarayana; Rajib Mall; Ajit Pal (Microprocess. Microsystems, 1996)

An Algorithm for Finding a Non-Trivial Lower Bound for Channel Routing. - Rajat Kumar Pal; Sudebkumar Prasant Pal; Ajit Pal (VLSI Design, 1997)

An algorithm for finding a non-trivial lower bound for channel routing1. - Rajat Kumar Pal; Sudebkumar Prasant Pal; Ajit Pal (Integr., 1998)

DDSCHED: A distributed dynamic real-time scheduling algorithm. - Anup K. Bhattacharjee; K. Ravindranath; Ajit Pal; Rajib Mall (Parallel Distributed Comput. Pract., 1998)

Deadline Assignment in Multiprocessor-Based Fault-Tolerant Systems. - Sharath Kumar Kodase; N. V. Satyanarayana; Ajit Pal; Rajib Mall (HiPC, 1999)

Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits. - Nikhil Tripathi; Amit M. Bhosle; Debasis Samanta; Ajit Pal (VLSI Design, 2001)

Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits. - Debasis Samanta; Ajit Pal (ASP-DAC/VLSI Design, 2002)

Synthesis of High Performance Low Power Dynamic CMOS Circuits. - Debasis Samanta; Nishant Sinha 001; Ajit Pal (ASP-DAC/VLSI Design, 2002)

Synthesis of high performance low power PTL circuits. - Debasis Samanta; M. C. Dharmadeep; Ajit Pal (ASP-DAC, 2003)

Synthesis of Dual-VT Dynamic CMOS Circuits. - Debasis Samanta; Ajit Pal (VLSI Design, 2003)

Routing and Wavelength Assignment in Wavelength Division Multiplexing Networks. - Ajit Pal; Umesh Patel (IWDC, 2004)

Energy-aware Logic Synthesis and Technology Mapping for MUX-based FPGAs. - Maitrali Marik; Ajit Pal (VLSI Design, 2004)

Synthesis of Low Power High Performance Dual-VT PTL Circuits. - Debasis Samanta; Ajit Pal (VLSI Design, 2004)

Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic. - Gopal Paul; Sambhu Nath Pradhan; Ajit Pal; Bhargab B. Bhattacharya (APCCAS, 2006)

On finding the minimum test set of a BDD-based circuit. - Gopal Paul; Ajit Pal; Bhargab B. Bhattacharya (ACM Great Lakes Symposium on VLSI, 2006)

Low Power Sensor Node for a Wireless Sensor Network. - Akepati Sravan; Sujan Kundu; Ajit Pal (VLSI Design, 2007)

Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations? - Sudip Roy 001; Ajit Pal (DSD, 2008)

Routing and Wavelength Assignment in All Optical Networks Based on Clique Partitioning. - Tanmay De; Ajit Pal; Indranil Sengupta 001 (ICDCN, 2008)

A Multi Objective Evolutionary Algorithm Based Approach for Traffic Grooming, Routing and Wavelength Assignment in Optical WDM Networks. - Tanmay De; Puneet Jain; Ajit Pal; Indranil Sengupta 001 (ICIIS, 2008)

A genetic algorithm based approach for traffic grooming, routing and wavelength assignment in optical WDM mesh networks. - Tanmay De; Puneet Jain; Ajit Pal; Indranil Sengupta 001 (ICON, 2008)

A power-aware wireless sensor network based bridge monitoring system. - Sujan Kundu; Sudip Roy 001; Ajit Pal (ICON, 2008)

Synthesis & Testing for Low Power. - Ajit Pal; Santanu Chattopadhyay (VLSI Design, 2009)

Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent. - Aritra Hazra; Srobona Mitra; Pallab Dasgupta; Ajit Pal; Debabrata Bagchi; Kaustav Guha (DAC, 2010)

Credit Reputation Propagation: A Strategy to Curb Free-Riding in a Large BitTorrent Swarm. - Suman Paul; Subrata Nandi; Ajit Pal (ICDCN, 2010)

Traffic grooming in WDM mesh networks using dynamic path selection strategy. - Sukanta Bhattacharya; Tanmay De; Ajit Pal (WOCN, 2010)

A New Technique for Runtime Leakage Reduction and Its Sensitivity and Parametric Yield Analysis Under Effective Channel-Length Variation. - Sudip Roy 001; Ajit Pal (J. Low Power Electron., 2010)

Traffic grooming, routing, and wavelength assignment in an optical WDM mesh networks based on clique partitioning. - Tanmay De; Ajit Pal; Indranil Sengupta 001 (Photonic Netw. Commun., 2010)

An Algorithm for Traffic Grooming in WDM Mesh Networks Using Dynamic Path Selection Strategy. - Sukanta Bhattacharya; Tanmay De; Ajit Pal (ICDCN, 2011)

Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design. - Mallikarjuna Rao Nimmagadda; Ajit Pal (ISVLSI, 2011)

Distributed dynamic grooming routing and wavelength assignment in WDM optical mesh networks. - Tanmay De; Puneet Jain; Ajit Pal (Photonic Netw. Commun., 2011)

Operator Scheduling Revisited: A Multi-objective Perspective for Fine-Grained DVS Architecture. - Rajdeep Mukherjee; Priyankar Ghosh; Pallab Dasgupta; Ajit Pal (ACITY (3), 2012)

Multi-objective Low-Power CDFG Scheduling Using Fine-Grained DVS Architecture in Distributed Framework. - Rajdeep Mukherjee; Priyankar Ghosh; N. Sravan Kumar; Pallab Dasgupta; Ajit Pal (ISED, 2012)

Branch Target Buffer Energy Reduction Through Efficient Multiway Branch Translation Techniques. - Sumanta Pyne; Ajit Pal (J. Low Power Electron., 2012)

Impact of Leakage Power Reduction Techniques on Parametric Yield - Low-Power Design of Digital Integrated Circuits under Process Parameter Variations. - Sudip Roy 001; Ajit Pal (LAP Lambert Academic Publishing, 2013)

Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence. - Sumanta Pyne; Ajit Pal (VDAT, 2013)

Formal Verification of Hardware / Software Power Management Strategies. - Rajdeep Mukherjee; Pallab Dasgupta; Ajit Pal; Subhankar Mukherjee 001 (VLSI Design, 2013)

A Multi-objective Perspective for Operator Scheduling using Fine-grained DVS Architecture - Rajdeep Mukherjee; Priyankar Ghosh; Pallab Dasgupta; Ajit Pal (CoRR, 2013)

An Integrated Approach for Fine-Grained Power and Peak Temperature Management During High-Level Synthesis. - Rajdeep Mukherjee; Priyankar Ghosh; Pallab Dasgupta; Ajit Pal (J. Low Power Electron., 2013)

POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent. - Aritra Hazra; Rajdeep Mukherjee; Pallab Dasgupta; Ajit Pal; Kevin Harer; Ansuman Banerjee; Subhankar Mukherjee 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Formal Verification of Architectural Power Intent. - Aritra Hazra; Sahil Goyal; Pallab Dasgupta; Ajit Pal (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Loop unrolling with fine grained power gating for runtime leakage power reduction. - Sumanta Pyne; Ajit Pal (VDAT, 2014)

A load balanced approach of multicast routing and wavelength assignment in WDM networks. - Subhendu Barat; Ajit Pal; Tanmay De (Int. J. Commun. Networks Distributed Syst., 2015)

Runtime Leakage Power Reduction Using Loop Unrolling and Fine Grained Power Gating. - Sumanta Pyne; Ajit Pal (J. Low Power Electron., 2015)

Energy Efficient Array Computations Using Loop Unrolling with Partial Gray Code Sequence. - Sumanta Pyne; Ajit Pal (J. Low Power Electron., 2015)

Extending light-trail into elastic optical networks for dynamic traffic grooming. - Prasanta Majumdar; Ajit Pal; Tanmay De (Opt. Switch. Netw., 2016)