ESD: a pervasive reliability concern for IC technologies. - Charvaka Duvvury; Ajith Amerasekera (Proc. IEEE, 1993)

A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities. - Prasun Raha; Scott Randall; Richard Jennings; Bob Helmick; Ajith Amerasekera; Baher Haroun (ISQED, 2002)

A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery. - Mike Harwood; Nirmal Warke; Richard Simpson 004; Tom Leslie; Ajith Amerasekera; Sean Batty; Derek Colman; Eugenia Carr; Venu Gopinathan; Steve Hubbins; Peter Hunt; Andy Joy; et al. (ISSCC, 2007)

Concurrent Optimization of Technology and Design for Nano CMOS. - Ajith Amerasekera (VLSI Design, 2007)

The Changing Design Landscape. - Ajith Amerasekera (IEEE Des. Test Comput., 2008)

Ultra low power electronics in the next decade. - Ajith Amerasekera (ISLPED, 2010)

Foreword. - Ajith Amerasekera; Makoto Nagata (VLSIC, 2012)

ES3: High-speed communications on 4 wheels: What's in your next car? - Nicola Da Dalt; Ajith Amerasekera (ISSCC, 2013)

A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems. - Masood Qazi; Ajith Amerasekera; Anantha P. Chandrakasan (ISSCC, 2013)

ES2: Data centers to support tomorrow's cloud. - Leland Chang; Ajith Amerasekera; Takashi Hashimoto (ISSCC, 2014)

A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-µm CMOS for Nonvolatile Processing in Digital Systems. - Masood Qazi; Ajith Amerasekera; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2014)

Session 10 overview: Advanced wireline techniques and PLLs: Wireline subcommittee. - Gerrit den Besten; Ajith Amerasekera (ISSCC, 2015)

Session 3 overview: Ultra-high-speed wireline transceivers and energy-efficient links. - Hyeon-Min Bae; Ajith Amerasekera (ISSCC, 2016)