Selection/Substitution of Visual Features for Object Tracking. - Ajith Pasqual; Kiyoharu Aizawa; Mitsutoshi Hatori (MVA, 1998)

Software Based Object Tracking with Visual Feature Integration. - Ajith Pasqual; Hidenori Takeshima; Kiyoharu Aizawa (ICIP (2), 1999)

Impact of ICT on learning and teaching. - Ravina Panangalage; Ajith Pasqual (ISTAS, 2008)

High performance parallel packet Classification architecture with Popular Rule Caching. - Samoda Gamage; Ajith Pasqual (ICON, 2012)

HEVC inverse transform architecture utilizing coefficient sparsity. - Maleen Abeydeera; Ajith Pasqual (ICIP, 2015)

Real time all intra HEVC HD encoder on FPGA. - Sachille Atapattu; Namitha Liyanage; Nisal Menuka; Ishantha Perera; Ajith Pasqual (ASAP, 2016)

High performance flow matching architecture for OpenFlow data plane. - Viduranga Bandara Wijekoon; T. M. Dananjaya; P. H. Kariyawasam; S. Iddamalgoda; Ajith Pasqual (NFV-SDN, 2016)

4K Real-Time HEVC Decoder on an FPGA. - Maleen Abeydeera; Manupa Karunaratne; Geethan Karunaratne; Kalana De Silva; Ajith Pasqual (IEEE Trans. Circuits Syst. Video Technol., 2016)

High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension. - Rishan Senanayake; Namitha Liyanage; Sasindu Wijeratne; Sachille Atapattu; Kasun Athukorala; P. M. K. Tharaka; Geethan Karunaratne; R. M. A. U. Senarath; Ishantha Perera; Ashen Ekanayake; Ajith Pasqual (ASAP, 2017)

Runtime rule-reconfigurable high throughput NIPS on FPGA. - P. M. K. Tharaka; D. M. D. Wijerathne; Navoda Perera; Dinushan Vishwajith; Ajith Pasqual (FPT, 2017)

Hybrid Software Defined Networking Controller. - Kosala Perera; Udesh Gunarathne; Binal Chathuranga; Chamika Ramanayake; Ajith Pasqual (DCNET, 2017)

FPAA and FPGA based universal sensor node design. - Ayanga D. Kalupahana; Nisal Hemadasa; Nipun Wijerathne; Anuranga Ranasinghe; Ajith Pasqual (ICST, 2017)

Reconfigurable Co-Processor Architecture with Limited Numerical Precision to Accelerate Deep Convolutiosnal Neural Networks. - Sasindu Wijeratne; Sandaruwan Jayaweera; Mahesh Dananjaya; Ajith Pasqual (ASAP, 2018)

A Novel Low-Complexity VLSI Architecture for an EEG Feature Extraction Platform. - Dakila Serasinghe; Duvindu Piyasena; Ajith Pasqual (DSD, 2018)

EdgeNet: SqueezeNet like Convolution Neural Network on Embedded FPGA. - Kathirgamaraja Pradeep; Kamalakkannan Kamalavasan; Ratnasegar Natheesan; Ajith Pasqual (ICECS, 2018)

SMPTE ST 2110 Compliant Scalable Architecture on FPGA for end to end Uncompressed Professional Video Transport Over IP Networks. - Nisal Ranasinghe; Ravindu Bangamuarachchi; Jayath Seneviratne; Achini Jayawardane; Ajith Pasqual; R. M. A. U. Senarath (ASAP, 2019)

Scalable High Performance SDN Switch Architecture on FPGA for Core Networks. - Sasindu Wijeratne; Ashen Ekanayake; Sandaruwan Jayaweera; Danuka Ravishan; Ajith Pasqual (FPGA, 2019)

FPGA IP for Real-time 4K HDR Image Decoding in VR Devices. - Kamlakannan Kamalavasan; Ratnasegar Natheesan; Kathirgamaraja Pradeep; Sivakumaran Gowthaman; Sivakaneshan Aravinth; Ajith Pasqual (LASCAS, 2019)

Reconfigurable co-processor architecture with limited numerical precision to accelerate deep convolutional neural networks. - Sasindu Wijeratne; Sandaruwan Jayaweera; Mahesh Dananjaya; Ajith Pasqual (CoRR, 2021)

A Four-Step Method to Synthesize a DC-DC Converter for Multi-Inductor Realizable Arbitrary Voltage Conversion Ratio. - Thilina S. Ambagahawaththa; Dulika Nayanasiri; Ajith Pasqual (IEEE Trans. Ind. Electron., 2022)