Akash Kumar

According to our database1, Akash Kumar authored at least 136 papers between 2002 and 2018.

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Bibliography

2018
A Hardware/Software Stack for Heterogeneous Systems.
IEEE Trans. Multi-Scale Computing Systems, 2018

Parallel FPGA Router using Sub-Gradient method and Steiner tree.
CoRR, 2018

CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems.
Proceedings of the 21st IEEE International Symposium on Real-Time Distributed Computing, 2018

Protecting Communication in Many-Core Systems against Active Attackers.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Dataflow-Based Mapping of Spiking Neural Networks on Neuromorphic Hardware.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and Scheduling.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Technology mapping flow for emerging reconfigurable silicon nanowire transistors.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Column Scan Optimization by Increasing Intra-Instruction Parallelism.
Proceedings of the 7th International Conference on Data Science, 2018

Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators.
Proceedings of the 55th Annual Design Automation Conference, 2018

SMApproxlib: library of FPGA-based approximate multipliers.
Proceedings of the 55th Annual Design Automation Conference, 2018

Lifetime-aware design methodology for dynamic partially reconfigurable systems.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Scrubbing Mechanism for Heterogeneous Applications in Reconfigurable Devices.
ACM Trans. Design Autom. Electr. Syst., 2017

Detection of pavement cracks using tiled fuzzy Hough transform.
J. Electronic Imaging, 2017

ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Exploiting transistor-level reconfiguration to optimize combinational circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Embracing approximate computing for energy-efficient motion estimation in high efficiency video coding.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Accounting for systematic errors in approximate computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Soft error-aware architectural exploration for designing reliability adaptive cache hierarchies in multi-cores.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Locality-Aware CTA Clustering for Modern GPUs.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016
Analysis and Mapping for Thermal and Energy Efficiency of 3-D Video Processing on 3-D Multicore Processors.
IEEE Trans. VLSI Syst., 2016

Reliability and Energy-Aware Mapping and Scheduling of Multimedia Applications on Multiprocessor Systems.
IEEE Trans. Parallel Distrib. Syst., 2016

Resource and Throughput Aware Execution Trace Analysis for Efficient Run-Time Mapping on MPSoCs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Leakage aware resource management approach with machine learning optimization framework for partially reconfigurable architectures.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

Machine Learning Approach to Generate Pareto Front for List-scheduling Algorithms.
Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, 2016

Automatic framework to generate reconfigurable accelerators for option pricing applications.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

X: A Comprehensive Analytic Model for Parallel Machines.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016

SFU-Driven Transparent Approximation Acceleration on GPUs.
Proceedings of the 2016 International Conference on Supercomputing, 2016

Architectural-space exploration of approximate multipliers.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

XNoC: A non-intrusive TDM circuit-switched Network-on-Chip.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Cross-layer fault-tolerant design of real-time systems.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

A flexible inexact TMR technique for SRAM-based FPGAs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Design and evaluation of reliability-oriented task re-mapping in MPSoCs using time-series analysis of intermittent faults.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Critical points based register-concurrency autotuning for GPUs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Autonomous Soft-Error Tolerance of FPGA Configuration Bits.
TRETS, 2015

Execution Trace-Driven Energy-Reliability Optimization for Multimedia MPSoCs.
TRETS, 2015

Nano-satellite swarm for SAR applications: design and robust scheduling.
IEEE Trans. Aerospace and Electronic Systems, 2015

Correlation ratio based volume image registration on GPUs.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Accelerating Non-volatile/Hybrid Processor Cache Design Space Exploration for Application Specific Embedded Systems.
CoRR, 2015

TRISHUL: A Single-pass Optimal Two-level Inclusive Data Cache Hierarchy Selection Process for Real-time MPSoCs.
CoRR, 2015

Adaptive and transparent cache bypassing for GPUs.
Proceedings of the International Conference for High Performance Computing, 2015

Hardware task migration module for improved fault tolerance and predictability.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Generic scrubbing-based architecture for custom error correction algorithms.
Proceedings of the 2015 International Symposium on Rapid System Prototyping, 2015

Fine-Grained Synchronizations and Dataflow Programming on GPUs.
Proceedings of the 29th ACM on International Conference on Supercomputing, 2015

Transit: A Visual Analytical Model for Multithreaded Machines.
Proceedings of the 24th International Symposium on High-Performance Parallel and Distributed Computing, 2015

An automated technique to generate relocatable partial bitstreams for Xilinx FPGAs.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

ParaLaR: A parallel FPGA router based on Lagrangian relaxation.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Designing inexact systems efficiently using elimination heuristics.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Dynamic reconfigurable puncturing for secure wireless communication.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Exploiting loop-array dependencies to accelerate the design space exploration with high level synthesis.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

(AS)2: accelerator synthesis using algorithmic skeletons for rapid design space exploration.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Workload uncertainty characterization and adaptive frequency scaling for energy minimization of embedded systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Dynamically adaptive scrubbing mechanism for improved reliability in reconfigurable embedded systems.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Accelerating non-volatile/hybrid processor cache design space exploration for application specific embedded systems.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Energy-aware task mapping and scheduling for reliable embedded computing systems.
ACM Trans. Embedded Comput. Syst., 2014

A Low Active Leakage and High Reliability Phase Change Memory (PCM) Based Non-Volatile FPGA Storage Element.
IEEE Trans. on Circuits and Systems, 2014

Communication and migration energy aware task mapping for reliable multiprocessor systems.
Future Generation Comp. Syst., 2014

MIPgen: optimized modeling and design of molecular inversion probes for targeted resequencing.
Bioinformatics, 2014

A multi-stage thermal management strategy for 3D multicores.
Proceedings of the 25nd IEEE International Symposium on Rapid System Prototyping, 2014

Lightweight Bare-Metal Stateful Firewall.
Proceedings of the 20th IEEE Pacific Rim International Symposium on Dependable Computing, 2014

A heterogeneous platform with GPU and FPGA for power efficient high performance computing.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Design and robust scheduling of nano-satellite swarm for synthetic aperture radar applications.
Proceedings of the 13th International Conference on Control Automation Robotics & Vision, 2014

A multi-stage leakage aware resource management technique for reconfigurable architectures.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Smart irrigation using low-cost moisture sensors and XBee-based communication.
Proceedings of the IEEE Global Humanitarian Technology Conference, 2014

FPGA-based high throughput XTS-AES encryption/decryption for storage area network.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Leakage and performance aware resource management for 2D dynamically reconfigurable FPGA architectures.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Multi-directional error correction schemes for SRAM-based FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

A bit-interleaved embedded hamming scheme to correct single-bit and multi-bit upsets for SRAM-based FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Criticality-aware scrubbing mechanism for SRAM-based FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

PR-HMPSoC: A versatile partially reconfigurable heterogeneous Multiprocessor System-on-Chip for dynamic FPGA-based embedded systems.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Design Space Exploration to Accelerate Nelder-Mead Algorithm Using FPGA.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Accelerating Volume Image Registration through Correlation Ratio Based Methods on GPUs.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Artificial intelligence based task mapping and pipelined scheduling for checkpointing on real time systems with imperfect fault detection.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Combined DVFS and mapping exploration for lifetime and soft-error susceptibility improvement in MPSoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Temperature aware energy-reliability trade-offs for mapping of throughput-constrained applications on multimedia MPSoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Reinforcement Learning-Based Inter- and Intra-Application Thermal Optimization for Lifetime Improvement of Multicore Systems.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Project-Based Learning in Embedded Systems Education Using an FPGA Platform.
IEEE Trans. Education, 2013

Computational analysis of xanthine dehydrogenase enzyme from different source organisms.
NetMAHIB, 2013

CADSE: communication aware design space exploration for efficient run-time MPSoC management.
Frontiers Comput. Sci., 2013

MAMPSx: A design framework for rapid synthesis of predictable heterogeneous MPSoCs.
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

Energy-aware dynamic reconfiguration of communication-centric applications for reliable MPSoCs.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

Real-time and low power embedded ℓ1-optimization solver design.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

MAMPSX: A demonstration of rapid, predictable HMPSOC synthesis.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

High Speed Video Processing Using Fine-Grained Processing on FPGA Platform.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Thermal-aware mapping of streaming applications on 3D Multi-Processor Systems.
Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013

RAPIDITAS: RAPId Design-Space-Exploration Incorporating Trace-Based Analysis and Simulation.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Incorporating Energy and Throughput Awareness in Design Space Exploration and Run-Time Mapping for Heterogeneous MPSoCs.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Run-time mapping for reliable many-cores based on energy/performance trade-offs.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Communication and migration energy aware design space exploration for multicore systems with intermittent faults.
Proceedings of the Design, Automation and Test in Europe, 2013

Reliability-driven task mapping for lifetime extension of networks-on-chip based multiprocessor systems.
Proceedings of the Design, Automation and Test in Europe, 2013

Mapping on multi/many-core systems: survey of current and emerging trends.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Energy optimization by exploiting execution slacks in streaming applications on multiprocessor systems.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Aging-aware hardware-software task partitioning for reliable reconfigurable multiprocessor systems.
Proceedings of the International Conference on Compilers, 2013

TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs.
ACM Trans. Design Autom. Electr. Syst., 2012

Review of polynomia and related realms by Dan Kalman.
SIGACT News, 2012

A design flow for partially reconfigurable heterogeneous multi-processor platforms.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

Fault-aware task re-mapping for throughput constrained multimedia applications on NoC-based MPSoCs.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

Fault-tolerant network interface for spatial division multiplexing based Network-on-Chip.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Energy-Aware Communication and Remapping of Tasks for Reliable Multimedia Multiprocessor Systems.
Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012

Development of an FPGA-based real-time P300 speller.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

An area-efficient partially reconfigurable crossbar switch with low reconfiguration delay.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Acceleration of distance-to-default with hardware-software co-design.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Minimizing Power Consumption of Spatial Division Based Networks-on-Chip Using Multi-path and Frequency Reduction.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Distributed resource management for concurrent execution of multimedia applications on MPSoC platforms.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Communication-Aware Design Space Exploration for Efficient Run-Time MPSoC Management.
Proceedings of the Fourth International Symposium on Parallel Architectures, 2011

A Design Space Exploration Methodology for Application Specific MPSoC Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Bringing soccer to the field of real-time embedded systems education.
Proceedings of the 6th Workshop on Embedded Systems Education, 2011

An Automated Flow to Map Throughput Constrained Applications to a MPSoC.
Proceedings of the Bringing Theory to Practice: Predictability and Performance in Embedded Systems, 2011

An MPSoC design approach for multiple use-cases of throughput constrainted applications.
Proceedings of the 8th Conference on Computing Frontiers, 2011

A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs.
Proceedings of the 14th International Conference on Compilers, 2011

2010
Iterative Probabilistic Performance Prediction for Multi-Application Multiprocessor Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Run-time mapping of multiple communicating tasks on MPSoC platforms.
Proceedings of the International Conference on Computational Science, 2010

Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms.
Journal of Systems Architecture - Embedded Systems Design, 2010

CA-MPSoC: An automated design flow for predictable multi-processor architectures for multiple applications.
Journal of Systems Architecture - Embedded Systems Design, 2010

An area-efficient dynamically reconfigurable Spatial Division Multiplexing network-on-chip with static throughput guarantee.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Mapping real-life applications on run-time reconfigurable NoC-based MPSoC on FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2010

A predictable communication assist.
Proceedings of the 7th Conference on Computing Frontiers, 2010

2009
Performance evaluation of concurrently executing parallel applications on multi-processor systems.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

2008
Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA.
ACM Trans. Design Autom. Electr. Syst., 2008

Analyzing composability of applications on MPSoC platforms.
Journal of Systems Architecture - Embedded Systems Design, 2008

Enabling MPSoC Design Space Exploration on FPGAs.
Proceedings of the Wireless Networks, 2008

Vectorization of Reed Solomon Decoding and Mapping on the EVP.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA.
Proceedings of the FPL 2007, 2007

Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices.
Proceedings of the 44th Design Automation Conference, 2007

2006
Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip.
Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, 2006

Global Analysis of Resource Arbitration for MPSoC.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005
Efficient techniques for improved QoS performance in WDM optical burst switched networks.
Computer Communications, 2005

2002
Membrane Systems and Distributed Computing.
Proceedings of the Membrane Computing, International Workshop, 2002


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