A pulsed sensing scheme with a limited bit-line swing. - Roy E. Scheuerlein; Yasunao Katayama; Toshiaki Kirihata; Yoshinori Sakaue; Akashi Satoh; Toshio Sunaga; T. Yoshikawa; Koji Kitamura; Sang H. Dhong (IEEE J. Solid State Circuits, 1992)

A 14-ns 14-Mb CMOS DRAM with 300-mW active power. - Toshiaki Kirihata; Sang H. Dhong; Koji Kitamura; Toshio Sunaga; Yasunao Katayama; Roy E. Scheuerlein; Akashi Satoh; Yoshinori Sakaue; Kentaroh Tobimatsu; Koji Hosokawa; Takaki Saitoh; Takefumi Yoshikawa; et al. (IEEE J. Solid State Circuits, 1992)

Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. - W. K. Luk; Yasunao Katayama; Wei Hwang; Matthew R. Wordeman; Toshiaki Kirihata; Akashi Satoh; Seiji Munetoh; Hing Wong; B. El-Kareh; P. Xiao; Rajiv V. Joshi (ICCD, 1997)

A High-Speed Small RSA Encryption LSI with Low Power Dissipation. - Akashi Satoh; Yoshinao Kobayashi; Hideto Niijima; Nobuyuki Ooba; Seiji Munetoh; Sadamichi Sone (ISW, 1997)

High-Speed MARS Hardware. - Akashi Satoh; Nobuyuki Ooba; Kohji Takano; Edward D'Avignon (AES Candidate Conference, 2000)

A Compact Rijndael Hardware Architecture with S-Box Optimization. - Akashi Satoh; Sumio Morioka; Kohji Takano; Seiji Munetoh (ASIACRYPT, 2001)

An Optimized S-Box Circuit Architecture for Low Power AES Design. - Sumio Morioka; Akashi Satoh (CHES, 2002)

Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI. - Akashi Satoh; Sumio Morioka (ISC, 2002)

Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia. - Akashi Satoh; Sumio Morioka (CHES, 2003)

Hardware-Focused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES. - Akashi Satoh; Sumio Morioka (ISC, 2003)

A Scalable Dual-Field Elliptic Curve Cryptographic Processor. - Akashi Satoh; Kohji Takano (IEEE Trans. Computers, 2003)

On-demand design service innovations. - Shigenori Shimizu; Hiroshi Ishikawa 008; Akashi Satoh; Toru Aihara (IBM J. Res. Dev., 2004)

A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. - Sumio Morioka; Akashi Satoh (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Hardware Architecture and Cost Estimates for Breaking SHA-1. - Akashi Satoh (ISC, 2005)

High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching. - Naofumi Homma; Sei Nagashima; Yuichi Imai; Takafumi Aoki; Akashi Satoh (CHES, 2006)

High-speed hardware architectures for authenticated encryption mode GCM. - Akashi Satoh (ISCAS, 2006)

SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier. - Atsushi Miyamoto; Naofumi Homma; Takafumi Aoki; Akashi Satoh (ISCAS, 2007)

DPA Using Phase-Based Waveform Matching against Random-Delay Countermeasure. - Sei Nagashima; Naofumi Homma; Yuichi Imai; Takafumi Aoki; Akashi Satoh (ISCAS, 2007)

High-Speed Parallel Hardware Architecture for Galois Counter Mode. - Akashi Satoh (ISCAS, 2007)

A High-Performance ASIC Implementation of the 64-bit Block Cipher CAST-128. - Takeshi Sugawara 001; Naofumi Homma; Takafumi Aoki; Akashi Satoh (ISCAS, 2007)

High-Speed Pipelined Hardware Architecture for Galois Counter Mode. - Akashi Satoh; Takeshi Sugawara 001; Takafumi Aoki (ISC, 2007)

ASIC-hardware-focused comparison for hash functions MD5, RIPEMD-160, and SHS. - Akashi Satoh; Tadanobu Inoue (Integr., 2007)

Collision-Based Power Analysis of Modular Exponentiation Using Chosen-Message Pairs. - Naofumi Homma; Atsushi Miyamoto; Takafumi Aoki; Akashi Satoh; Adi Shamir (CHES, 2008)

High-Performance Concurrent Error Detection Scheme for AES Hardware. - Akashi Satoh; Takeshi Sugawara 001; Naofumi Homma; Takafumi Aoki (CHES, 2008)

Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems. - Yohei Hori; Akashi Satoh; Hirofumi Sakane; Kenji Toda (FPL, 2008)

Chosen-message SPA attacks against FPGA-based RSA hardware implementations. - Atsushi Miyamoto; Naofumi Homma; Takafumi Aoki; Akashi Satoh (FPL, 2008)

Systematic design of high-radix Montgomery multipliers for RSA processors. - Atsushi Miyamoto; Naofumi Homma; Takafumi Aoki; Akashi Satoh (ICCD, 2008)

Enhanced power analysis attack using chosen message against RSA hardware implementations. - Atsushi Miyamoto; Naofumi Homma; Takafumi Aoki; Akashi Satoh (ISCAS, 2008)

ASIC hardware implementations for 512-bit hash function Whirlpool. - Akashi Satoh (ISCAS, 2008)

High-performance ASIC implementations of the 128-bit block cipher CLEFIA. - Takeshi Sugawara 001; Naofumi Homma; Takafumi Aoki; Akashi Satoh (ISCAS, 2008)

Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems. - Yohei Hori; Akashi Satoh; Hirofumi Sakane; Kenji Toda (IWSEC, 2008)

Enhanced Correlation Power Analysis Using Key Screening Technique. - Toshihiro Katashita; Akashi Satoh; Takeshi Sugawara 001; Naofumi Homma; Takafumi Aoki (ReConFig, 2008)

Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool. - Takeshi Sugawara 001; Naofumi Homma; Takafumi Aoki; Akashi Satoh (WISA, 2008)

A High-Resolution Phase-Based Waveform Matching and Its Application to Side-Channel Attacks. - Naofumi Homma; Sei Nagashima; Takeshi Sugawara 001; Takafumi Aoki; Akashi Satoh (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques. - Minoru Saeki; Daisuke Suzuki; Koichi Shimizu; Akashi Satoh (CHES, 2009)

Development of side-channel attack standard evaluation environment. - Toshihiro Katashita; Akashi Satoh; Takeshi Sugawara 001; Naofumi Homma; Takafumi Aoki (ECCTD, 2009)

Differential power analysis of AES ASIC implementations with various S-box circuits. - Takeshi Sugawara 001; Naofumi Homma; Takafumi Aoki; Akashi Satoh (ECCTD, 2009)

Evaluation of Simple/Comparative Power Analysis against an RSA ASIC Implementation. - Atsushi Miyamoto; Naofumi Homma; Takafumi Aoki; Akashi Satoh (ISCAS, 2009)

Compact and High-speed Hardware Architectures for Hash Function Tiger. - Akashi Satoh; Nicolas Sklavos 001 (ISCAS, 2009)

Is the differential frequency-based attack effective against random delay insertion? - Yingxi Lu; Keanhong Boey; Máire O'Neill; John V. McCanny; Akashi Satoh (SiPS, 2009)

Mechanism behind Information Leakage in Electromagnetic Analysis of Cryptographic Modules. - Takeshi Sugawara 001; Yu-ichi Hayashi; Naofumi Homma; Takaaki Mizuki; Takafumi Aoki; Hideaki Sone; Akashi Satoh (WISA, 2009)

High-Performance Hardware Architectures for Galois Counter Mode. - Akashi Satoh; Takeshi Sugawara 001; Takafumi Aoki (IEEE Trans. Computers, 2009)

Prototyping Platform for Performance Evaluation of SHA-3 Candidates. - Kazuyuki Kobayashi; Jun Ikegami; Kazuo Sakiyama; Kazuo Ohta; Miroslav Knezevic; Ünal Koçabas; Junfeng Fan; Ingrid Verbauwhede; Eric Xu Guo; Shin'ichiro Matsuo; Sinan Huang; Leyla Nazhandali; et al. (HOST, 2010)

Hardware Implementations of Hash Function Luffa. - Akashi Satoh; Toshihiro Katashita; Takeshi Sugawara 001; Naofumi Homma; Takafumi Aoki (HOST, 2010)

Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs. - Yohei Hori; Takahiro Yoshida; Toshihiro Katashita; Akashi Satoh (ReConFig, 2010)

Profiling attack using multivariate regression analysis. - Takeshi Sugawara 001; Naofumi Homma; Takafumi Aoki; Akashi Satoh (IEICE Electron. Express, 2010)

A Design Methodology for a DPA-Resistant Circuit with RSL Techniques. - Daisuke Suzuki; Minoru Saeki; Koichi Shimizu; Akashi Satoh; Tsutomu Matsumoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Comparative Power Analysis of Modular Exponentiation Algorithms. - Naofumi Homma; Atsushi Miyamoto; Takafumi Aoki; Akashi Satoh; Adi Shamir (IEEE Trans. Computers, 2010)

A fast power current analysis methodology using capacitor charging model for side channel attack evaluation. - Daisuke Fujimoto; Makoto Nagata; Toshihiro Katashita; Akihiro T. Sasaki; Yohei Hori; Akashi Satoh (HOST, 2011)

Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function. - Yohei Hori; Hyunho Kang; Toshihiro Katashita; Akashi Satoh (ReConFig, 2011)

High-Performance Architecture for Concurrent Error Detection for AES Processors. - Takeshi Sugawara 001; Naofumi Homma; Takafumi Aoki; Akashi Satoh (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

An on-chip glitchy-clock generator for testing fault injection attacks. - Sho Endo; Takeshi Sugawara 001; Naofumi Homma; Takafumi Aoki; Akashi Satoh (J. Cryptogr. Eng., 2011)

Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers. - Atsushi Miyamoto; Naofumi Homma; Takafumi Aoki; Akashi Satoh (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A Configurable On-Chip Glitchy-Clock Generator for Fault Injection Experiments. - Sho Endo; Takeshi Sugawara 001; Naofumi Homma; Takafumi Aoki; Akashi Satoh (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Evaluation of Information Leakage from Cryptographic Hardware via Common-Mode Current. - Yu-ichi Hayashi; Naofumi Homma; Takaaki Mizuki; Takeshi Sugawara 001; Yoshiki Kayano; Takafumi Aoki; Shigeki Minegishi; Akashi Satoh; Hideaki Sone; Hiroshi Inoue (IEICE Trans. Electron., 2012)

Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates. - Miroslav Knezevic; Kazuyuki Kobayashi; Jun Ikegami; Shin'ichiro Matsuo; Akashi Satoh; Ünal Koçabas; Junfeng Fan; Toshihiro Katashita; Takeshi Sugawara 001; Kazuo Sakiyama; Ingrid Verbauwhede; Kazuo Ohta; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation. - Daisuke Fujimoto; Toshihiro Katashita; Akihiko Sasaki; Yohei Hori; Akashi Satoh; Makoto Nagata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption. - Yohei Hori; Toshihiro Katashita; Hirofumi Sakane; Kenji Toda; Akashi Satoh (IEICE Trans. Inf. Syst., 2013)

Side-channel AttacK User Reference Architecture board SAKURA-G. - Hendra Guntur; Jun Ishii; Akashi Satoh (GCCE, 2014)

FPGA implementation of new standard hash function Keccak. - Tatsuya Honda; Hendra Guntur; Akashi Satoh (GCCE, 2014)

Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays. - Yohei Hori; Hyunho Kang; Toshihiro Katashita; Akashi Satoh; Shin-ichi Kawamura; Kazukuni Kobara (J. Inf. Process., 2014)

FPGA implementation of authenticated encryption algorithm Minalpher. - Makiko Kosug; Masahiro Yasuda; Akashi Satoh (GCCE, 2015)

Side-channel Attack user reference architecture board SAKURA-W for security evaluation of IC card. - Masato Matsubayashi; Akashi Satoh (GCCE, 2015)

GPGPU software implementation of authenticated encryption algorithm Minalpher. - Makiko Kosugi; Akashi Satoh (GCCE, 2016)

Clock glitch generator on SAKURA-G for fault injection attack against a cryptographic circuit. - Masato Matsubayashi; Akashi Satoh; Jun Ishii (GCCE, 2016)

High-accuracy and low-cost sensor module for hydroponic culture system. - Tomohiro Nishimura; Yuji Okuyama; Akashi Satoh (GCCE, 2016)

Comparison of side-channel attack on cryptographic cirucits between old and new technology FPGAs. - Yu Nomata; Masato Matsubayashi; Kohei Sawada; Akashi Satoh (GCCE, 2016)

Security evaluation of cryptographic modules against side-channel attack using a biased data set. - Masato Matsubayashi; Hendra Guntur; Akashi Satoh (GCCE, 2017)

A compact hardware design of a sensor module for hydroponics. - Tomohiro Nishimura; Yuji Okuyama; Ayaka Matsushita; Hiromichi Ikeda; Akashi Satoh (GCCE, 2017)

A Hydroponic Planter System to enable an Urban Agriculture Service Industry. - Akashi Satoh (GCCE, 2018)

Fertilizer Management System for A Compact Hydroponic Planter. - Kaori Uehara; Hiromichi Ikeda; Akashi Satoh (GCCE, 2019)

Development of Hornet Detection Camera System for Smart Beekeeping. - Mitsuki Terada; Akashi Satoh (GCCE, 2022)

Non intrusive current and power factor sensor with energy harvesting for maintenance-free operation. - Takaya Yoshitake; Akashi Satoh; Shinichiro Mito (IEEE SENSORS, 2022)