Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost. - Akhil Garg 001; Prashant Dubey (DFT, 2006)

Built in Defect Prognosis for Embedded Memories. - Prashant Dubey; Akhil Garg 001; Sravan Kumar Bhaskarani (DDECS, 2007)

GALS Based Shared Test Architecture for Embedded Memories. - Prashant Dubey; Akhil Garg 001; Sravan Kumar Bhaskarani (ISCAS, 2007)

Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase Prognosis. - Prashant Dubey; Akhil Garg 001; Sravan Kumar Bhaskarani (ISVLSI, 2007)

On Chip Jitter Measurement through a High Accuracy TDC. - Akhil Garg 001; Prashant Dubey (ISQED, 2008)

Low Power Test. - Swapnil Bahl; Rajiv Sarkar; Akhil Garg 001 (ITC, 2008)

Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time. - Prashant Dubey; Akhil Garg 001; Shashank Mahajan (J. Electron. Test., 2010)

State of the art low capture power methodology. - Swapnil Bahl; Roberto Mattiuzzo; Shray Khullar; Akhil Garg 001; S. Graniello; Khader S. Abdel-Hafez; Salvatore Talluto 001 (ITC, 2011)

SmartScan - Hierarchical test compression for pin-limited low power designs. - Krishna Chakravadhanula; Vivek Chickermane; Don Pearl; Akhil Garg 001; R. Khurana; Subhasish Mukherjee; P. Nagaraj (ITC, 2013)

Efficient testing of hierarchical core-based SOCs. - Brion L. Keller; Krishna Chakravadhanula; Brian Foutz; Vivek Chickermane; Akhil Garg 001; Richard Schoonover; James Sage; Don Pearl; Thomas J. Snethen (ITC, 2014)