Delay estimation, chip-power analyses and comparison of single-level and multi-level recursive vedic algorithm with conventional algorithms for digital multiplier. - Dipankar Pal; Akhilesh G. Naik (ICICDT, 2018)

ASIC Implementation of High-Speed Adaptive Recursive Karatsuba Multiplier with Square-Root-Carry-Select-Adder. - Akhilesh G. Naik; Debarshi Deka; Dipankar Pal (LASCAS, 2020)