A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals. - Akihide Sai; Daisuke Kurose; Takafumi Yamaji; Tetsuro Itakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A 570fsrms integrated-jitter ring-VCO-based 1.21GHz PLL with hybrid loop. - Akihide Sai; Takafumi Yamaji; Tetsuro Itakura (ISSCC, 2011)

A 2Gb/s-throughput CMOS transceiver chipset with in-package antenna for 60GHz short-range wireless communication. - Toshiya Mitomo; Yukako Tsutsumi; Hiroaki Hoshino; Masahiro Hosoya; Tong Wang 018; Yuta Tsubouchi; Ryoichi Tachibana; Akihide Sai; Yuka Kobayashi; Daisuke Kurose; Tomohiko Ito; Koichiro Ban; et al. (ISSCC, 2012)

A digitally stabilized type-III PLL using ring VCO with 1.01psrms integrated jitter in 65nm CMOS. - Akihide Sai; Yuka Kobayashi; Shigehito Saigusa; Osamu Watanabe 003; Tetsuro Itakura (ISSCC, 2012)

A 2-Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60-GHz Short-Range Wireless Communication. - Toshiya Mitomo; Yukako Tsutsumi; Hiroaki Hoshino; Masahiro Hosoya; Tong Wang 018; Yuta Tsubouchi; Ryoichi Tachibana; Akihide Sai; Yuka Kobayashi; Daisuke Kurose; Tomohiko Ito; Koichiro Ban; et al. (IEEE J. Solid State Circuits, 2012)

Correction to "A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication". - Toshiya Mitomo; Yukako Tsutsumi; Hiroaki Hoshino; Masahiro Hosoya; Tong Wang 018; Yuta Tsubouchi; Ryoichi Tachibana; Akihide Sai; Yuka Kobayashi; Daisuke Kurose; Tomohiko Ito; Koichiro Ban; et al. (IEEE J. Solid State Circuits, 2013)

20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication. - Shigehito Saigusa; Toshiya Mitomo; Hidenori Okuni; Masahiro Hosoya; Akihide Sai; Shusuke Kawai; Tong Wang 018; Masanori Furuta; Kei Shiraishi; Koichiro Ban; Seiichiro Horikawa; Tomoya Tandai; et al. (ISSCC, 2014)

A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS. - Masanori Furuta; Hidenori Okuni; Masahiro Hosoya; Akihide Sai; Junya Matsuno; Shigehito Saigusa; Tetsuro Itakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS. - Hidenori Okuni; Akihide Sai; Tuan Thanh Ta; Satoshi Kondo; Takashi Tokairin; Masanori Furuta; Tetsuro Itakura (ISSCC, 2016)

19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC. - Akihide Sai; Satoshi Kondo; Tuan Thanh Ta; Hidenori Okuni; Masanori Furuta; Tetsuro Itakura (ISSCC, 2016)

A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS. - Akihide Sai; Hidenori Okuni; Tuan Thanh Ta; Satoshi Kondo; Takashi Tokairin; Masanori Furuta; Tetsuro Itakura (IEEE J. Solid State Circuits, 2016)

28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique. - Kentaro Yoshioka; Tomohiko Sugimoto; Naoya Waki; Sinnyoung Kim; Daisuke Kurose; Hirotomo Ishii; Masanori Furuta; Akihide Sai; Tetsuro Itakura (ISSCC, 2017)

A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications. - Yosuke Toyama; Kentaro Yoshioka; Koichiro Ban; Akihide Sai; Kohei Onizuka (A-SSCC, 2018)

Data selection and de-noising based on reliability for long-range and high-pixel resolution LiDAR. - Ken Tanabe; Hiroshi Kubota; Akihide Sai; Nobu Matsumoto (COOL CHIPS, 2018)

A 15mW -105dBm Image-Sparse-Sliding-IF Receiver with Transformer-Based on-Chip Q-Enhanced RF Matching Network for a 113dB-Link-Budget BLE 5.0 TRX. - Tuan Thanh Ta; Yosuke Ogasawara; Tong Wang 018; Masayoshi Oshiro; Naotaka Koide; Akihide Sai; Takashi Tokairin (ESSCIRC, 2018)

A 20ch TDC/ADC hybrid SoC for 240×96-pixel 10%-reflection <0.125%-precision 200m-range imaging LiDAR with smart accumulation technique. - Kentaro Yoshioka; Hiroshi Kubota; Tomonori Fukushima; Satoshi Kondo; Tuan Thanh Ta; Hidenori Okuni; Kaori Watanabe; Yoshinari Ojima; Katsuyuki Kimura; Sohichiroh Hosoda; Yutaka Ota; Tomohiro Koizumi; et al. (ISSCC, 2018)

An 113DB-Link-Budget Bluetooth-5 SoC with an 8dBm 22%-Efficiency TX. - Tong Wang 018; Yosuke Ogasawara; Yuki Tuda; Tuan Thanh Ta; Masayoshi Oshiro; Jun Ihara; Tatsuhiko Maruyama; Toru Hashimoto; Akihide Sai; Takashi Tokairin (VLSI Circuits, 2018)

PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators. - Kentaro Yoshioka; Yosuke Toyama; Koichiro Ban; Daisuke Yashima; Shigeru Maya; Akihide Sai; Kohei Onizuka (VLSI Circuits, 2018)

A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 × 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC. - Kentaro Yoshioka; Hiroshi Kubota; Tomonori Fukushima; Satoshi Kondo; Tuan Thanh Ta; Hidenori Okuni; Kaori Watanabe; Masatoshi Hirono; Yoshinari Ojima; Katsuyuki Kimura; Sohichiroh Hosoda; Yutaka Ota; et al. (IEEE J. Solid State Circuits, 2018)

Inter-Frame Smart-Accumulation Technique for Long-Range and High-Pixel Resolution LiDAR. - Ken Tanabe; Hiroshi Kubota; Akihide Sai; Nobu Matsumoto (COOL CHIPS, 2019)

An 8 Bit 12.4 TOPS/W Phase-Domain MAC Circuit for Energy-Constrained Deep Learning Accelerators. - Yosuke Toyama; Kentaro Yoshioka; Koichiro Ban; Shigeru Maya; Akihide Sai; Kohei Onizuka (IEEE J. Solid State Circuits, 2019)

Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits. - Kentaro Yoshioka; Tomohiko Sugimoto; Naoya Waki; Sinnyoung Kim; Daisuke Kurose; Hirotomo Ishii; Masanori Furuta; Akihide Sai; Hiroki Ishikuro; Tetsuro Itakura (IEEE Trans. Very Large Scale Integr. Syst., 2019)

5.1 A 240×192 Pixel 10fps 70klux 225m-Range Automotive LiDAR SoC Using a 40ch 0.0036mm2 Voltage/Time Dual-Data-Converter-Based AFE. - Satoshi Kondo; Hiroshi Kubota; Hisaaki Katagiri; Yutaka Ota; Masatoshi Hirono; Tuan Thanh Ta; Hidenori Okuni; Shinichi Ohtsuka; Yoshinari Ojima; Tomohiko Sugimoto; Hirotomo Ishii; Kentaro Yoshioka; et al. (ISSCC, 2020)

A 2D-SPAD Array and Read-Out AFE for Next-Generation Solid-State LiDAR. - Tuan Thanh Ta; Hiroshi Kubota; Koichi Kokubun; Toshiki Sugimoto; Masatoshi Hirono; Mitsuhiro Sengoku; Hisaaki Katagiri; Hidenori Okuni; Satoshi Kondo; Shinichi Ohtsuka; Honam Kwon; Keita Sasaki; et al. (VLSI Circuits, 2020)

An Automotive LiDAR SoC for 240 × 192-Pixel 225-m-Range Imaging With a 40-Channel 0.0036-mm2 Voltage/Time Dual-Data-Converter-Based AFE. - Satoshi Kondo; Hiroshi Kubota; Hisaaki Katagiri; Yutaka Ota; Masatoshi Hirono; Tuan Thanh Ta; Hidenori Okuni; Shinichi Ohtsuka; Yoshinari Ojima; Tomohiko Sugimoto; Hirotomo Ishii; Kentaro Yoshioka; et al. (IEEE J. Solid State Circuits, 2020)

Through the Looking Glass: Diminishing Occlusions in Robot Vision Systems with Mirror Reflections. - Kentaro Yoshioka; Hidenori Okuni; Tuan Thanh Ta; Akihide Sai (IROS, 2021)

1200x84-pixels 30fps 64cc Solid-State LiDAR RX with an HV/LV transistors Hybrid Active-Quenching-SPAD Array and Background Digital PT Compensation. - Toshiki Sugimoto; Tuan Thanh Ta; Koichi Kokubun; Satoshi Kondo; Tetsuro Itakura; Hisaaki Katagiri; Yutaka Ota; Mitsuhiro Sengoku; Honam Kwon; Keita Sasaki; Hiroshi Kubota; Kazuhiro Suzuki; et al. (VLSI Technology and Circuits, 2022)