0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file. - Hiroyuki Hara; Takayasu Sakurai; Tetsu Nagamatsu; Katsuhiro Seta; Hiroshi Momose; Yoichirou Niitsu; Hiroyuki Miyakawa; Kouji Matsuda; Yoshinori Watanabe; Fumihiko Sano; Akihiko Chiba (IEEE J. Solid State Circuits, 1992)

A 200 MHz 13 mm2 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme. - Masataka Matsui; Hiroyuki Hara; Yoshiharu Uetani; Lee-Sup Kim; Tetsu Nagamatsu; Yoshinori Watanabe; Akihiko Chiba; Kouji Matsuda; Takayasu Sakurai (IEEE J. Solid State Circuits, 1994)

A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme. - Mototsugu Hamada; Masafumi Takahashi; Hideho Arakida; Akihiko Chiba; Toshihiro Terazawa; Takashi Ishikawa; Masahiro Kanazawa; Mutsunori Igarashi; Kimiyoshi Usami; Tadahiro Kuroda (CICC, 1998)

Variable supply-voltage scheme for low-power high-speed CMOS digital design. - Tadahiro Kuroda; Kojiro Suzuki; Shinji Mita; Tetsuya Fujita; Fumiyuki Yamane; Fumihiko Sano; Akihiko Chiba; Yoshinori Watanabe; Koji Matsuda; Takeo Maeda; Takayasu Sakurai; Tohru Furuyama (IEEE J. Solid State Circuits, 1998)

A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. - Masafumi Takahashi; Mototsugu Hamada; Tsuyoshi Nishikawa; Hideho Arakida; Tetsuya Fujita; Fumitoshi Hatori; Shinji Mita; Kojiro Suzuki; Akihiko Chiba; Toshihiro Terazawa; Fumihiko Sano; Yoshinori Watanabe; et al. (IEEE J. Solid State Circuits, 1998)