A 2/3-in 2 million pixel STACK-CCD HDTV imager. - Hirofumi Yamashita; Michio Sasaki; Shinji Ohsawa; Ryohei Miyagawa; Eiji Ohba; Keiji Mabuchi; Nobuo Nakamura; Nagataka Tanaka; Nahoko Endoh; Ikuko Inoue; Yoshiyuki Matsunaga; Yoshitaka Egawa; et al. (IEEE J. Solid State Circuits, 1995)

A 2.4-GHz-band 1.8-V operation single-chip Si-CMOS T/R-MMIC front-end with a low insertion loss switch. - Kazuya Yamamoto; Tetsuya Heima; Akihiko Furukawa; Masayoshi Ono; Yasushi Hashizume; Hiroshi Komurasaki; Shigenobu Maeda; Hisayasu Sato; Naoyuki Kato (IEEE J. Solid State Circuits, 2001)

2.4-GHz-Band CMOS RF Front-End Building Blocks at a 1.8-V Supply. - Hiroshi Komurasaki; Kazuya Yamamoto; Hideyuki Wakada; Tetsuya Heima; Akihiko Furukawa; Hisayasu Sato; Takahiro Miki; Naoyuki Kato; Akira Hyogo; Keitaro Sekine (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

21.5-dBm power-handling 5-GHz transmit/receive CMOS switch realized by voltage division effect of stacked transistor configuration with depletion-layer-extended transistors (DETs). - Takahiro Ohnakado; Satoshi Yamakawa; Takaaki Murakami; Akihiko Furukawa; Eiji Taniguchi; Hiro-omi Ueda; Noriharu Suematsu; Tatsuo Oomori (IEEE J. Solid State Circuits, 2004)