A 1.3GHz fifth generation SPARC64 microprocessor. - Hisashige Ando; Yuuji Yoshida; Aiichiro Inoue; Itsumi Sugiyama; Takeo Asakawa; Kuniki Morita; Toshiyuki Muta; Tsuyoshi Motokurumada; Seishi Okada; Hideo Yamashita; Yoshihiko Satsukawa; Akihiko Konmoto; et al. (DAC, 2003)

A 1.3-GHz fifth-generation SPARC64 microprocessor. - Hisashige Ando; Yuuji Yoshida; Aiichiro Inoue; Itsumi Sugiyama; Takeo Asakawa; Kuniki Morita; Toshiyuki Muta; Tsuyoshi Motokurumada; Seishi Okada; Hideo Yamashita; Yoshihiko Satsukawa; Akihiko Konmoto; et al. (IEEE J. Solid State Circuits, 2003)

A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution. - Takushi Hashida; Yasumoto Tomita; Yuuki Ogata; Kosuke Suzuki; Shigeto Suzuki; Takanori Nakao; Yuji Terao; Satofumi Honda; Sota Sakabayashi; Ryuichi Nishiyama; Akihiko Konmoto; Yoshitomo Ozeki; et al. (VLSIC, 2014)