Low-power nanophotonic devices based on photonic crystals towards dense photonic network on chip. - Masaya Notomi; Akihiko Shinya; Kengo Nozaki; Takasumi Tanabe; Shinji Matsuo; Eiichi Kuramochi; Tomonari Sato; Hideaki Taniyama; Hisashi Sumikura (IET Circuits Devices Syst., 2011)

High-Temperature Operation of Photonic-Crystal Lasers for On-Chip Optical Interconnection. - Koji Takeda; Tomonari Sato; Takaaki Kakitsuka; Akihiko Shinya; Kengo Nozaki; Chin-Hui Chen; Hideaki Taniyama; Masaya Notomi; Shinji Matsuo (IEICE Trans. Electron., 2012)

Integrated on-chip optical links using photonic-crystal lasers and photodetectors with current blocking trenches. - Koji Takeda; Tomonari Sato; Akihiko Shinya; Kengo Nozaki; Hideaki Taniyama; Masaya Notomi; Koichi Hasebe; Takaaki Kakitsuka; Shinji Matsuo (OFC/NFOEC, 2013)

Femtojoule/bit integrated nanophotonics based on photonic crystals. - Masaya Notomi; Kengo Nozaki; Akihiko Shinya; Shinji Matsuo; Eiichi Kuramochi (IEICE Electron. Express, 2013)

25-Gbit/s direct modulation of photonic-crystal lasers with a 10.5-fJ/bit energy cost for on/off-chip optical interconnects. - Koji Takeda; Tomonari Sato; Takuro Fujii; Akihiko Shinya; Eiichi Kuramochi; Masaya Notomi; Koichi Hasebe; Takaaki Kakitsuka; Shinji Matsuo (ECOC, 2014)

Ultralow-power and integrated operation of all-optical switches/memories in a photonic crystal chip. - Kengo Nozaki; Eiichi Kuramochi; Akihiko Shinya; Shinji Matsuo; Tomonari Sato; Masaya Notomi (ICTON, 2014)

An integrated optical parallel adder as a first step towards light speed data processing. - Tohru Ishihara; Akihiko Shinya; Koji Inoue; Kengo Nozaki; Masaya Notomi (ISOCC, 2016)

1-fJ/bit Direct Modulation of Photonic-Crystal Lasers. - Koji Takeda; Takuro Fujii; Akihiko Shinya; Masaya Notomi; Takaaki Kakitsuka; Shinji Matsuo (ECOC, 2018)

Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics. - Takumi Egawa; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Shota Kita; Kengo Nozaki; Kenta Takata; Masaya Notomi (ICRC, 2018)

An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (ICRC, 2018)

Femto-Farad Optoelectronic Coupling and Low-Latency Nanophotonic Computing. - Kengo Nozaki; Shota Kita; Akihiko Shinya (ICTON, 2018)

An Integrated Nanophotonic Parallel Adder. - Tohru Ishihara; Akihiko Shinya; Koji Inoue; Kengo Nozaki; Masaya Notomi (ACM J. Emerg. Technol. Comput. Syst., 2018)

BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing. - Ryosuke Matsuo; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (ASP-DAC, 2019)

A 300-mm-wafer silicon photonics technology for advanced information systems. - Koji Yamada; Guangwei Cong; Makoto Okano; Yuriko Maegami; Morifumi Ohno; Keijiro Suzuki; Satoshi Suda; Ryotaro Konoike; Kazuhiro Ikeda; Hitoshi Kawashima; Tsuyoshi Horikawa; Shu Namiki; et al. (ISDCS, 2019)

An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator. - Tohru Ishihara; Jun Shiomi; Naoki Hattori; Yutaka Masuda; Akihiko Shinya; Masaya Notomi (PHOTONICS@SC, 2019)

Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits. - Ryosuke Matsuo; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (ICRC, 2020)

A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing. - Ryosuke Matsuo; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (ISVLSI, 2020)

Femto-Farad Nanophotonic Devices for fJ/Bit Signal Conversion. - Kengo Nozaki; Shinji Matsuo; Takuro Fujii; Koji Takeda; Eiichi Kuramochi; Akihiko Shinya; Masaya Notomi (OFC, 2020)

Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics. - Jun Shiomi; Shuya Kotsugi; Boyu Dong; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (DAC, 2021)

Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation. - Naoki Hattori; Jun Shiomi; Yutaka Masuda; Tohru Ishihara; Akihiko Shinya; Masaya Notomi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits. - Ryosuke Matsuo; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

Power-aware pruning for ultrafast, energy-efficient, and accurate optical neural network design. - Naoki Hattori; Yutaka Masuda; Tohru Ishihara; Akihiko Shinya; Masaya Notomi (DAC, 2022)

Optoelectronic Implementation of Compact and Power-efficient Recurrent Neural Networks. - Taisei Ichikawa; Yutaka Masuda; Tohru Ishihara; Akihiko Shinya; Masaya Notomi (ISVLSI, 2022)

Energy efficient OEO conversion and its applications to photonic integrated systems. - Akihiko Shinya; Kengo Nozaki; Shota Kita; Tohru Ishihara; Shinji Matsuo; Masaya Notomi (OFC, 2022)