Investigating heterogeneous combination of functional units for a criticality-based low-power processor architecture. - Akihiro Chiyonobu; Toshinori Sato (ISICT, 2004)

An Energy-Efficient Clustered Superscalar Processor. - Toshinori Sato; Akihiro Chiyonobu (IEICE Trans. Electron., 2005)

Improving Energy Efficiency Via Speculative Multithreading on MultiCore Processors. - Toshinori Sato; Yuu Tanaka; Hidenori Sato; Toshimasa Funaki; Takenori Koushiro; Akihiro Chiyonobu (PATMOS, 2006)

Evaluating the Impact of Fault Recovery on Superscalar Processor Performance. - Toshinori Sato; Akihiro Chiyonobu (PRDC, 2006)

A leakage-energy-reduction technique for cache memories in embedded processors. - Seiichiri Fujii; Akihito Sakanaka; Akihiro Chiyonobu; Toshinori Sato (J. Embed. Comput., 2006)

Energy-efficient instruction scheduling utilizing cache miss information. - Akihiro Chiyonobu; Toshinori Sato (SIGARCH Comput. Archit. News, 2006)

Indirect Tag Search Mechanism for Instruction Window Energy Reduction. - Shingo Watanabe; Akihiro Chiyonobu; Toshinori Sato (CIT, 2007)

Challenges in Evaluations for a Typical-Case Design Methodology. - Yuji Kunitake; Akihiro Chiyonobu; Koichiro Tanaka; Toshinori Sato (ISQED, 2007)

Realizing Energy-Efficient MultiCore Processors by Utilizing Speculative Thread-Level Parallelism. - Toshinori Sato; Yuu Tanaka; Hidenori Sato; Toshimasa Funaki; Takenori Koushiro; Akihiro Chiyonobu (Int. J. Comput. Their Appl., 2007)

A Low-Power Instruction Issue Queue for Microprocessors. - Shingo Watanabe; Akihiro Chiyonobu; Toshinori Sato (IEICE Trans. Electron., 2008)